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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / schizo / include / schizo_impl.h
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920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: schizo_impl.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright (C) 1996, 2001 Sun Microsystems, Inc.
25 * All rights reserved.
26 */
27#ifndef _SCHIZO_IMPL_H
28#define _SCHIZO_IMPL_H
29
30
31
32#include <synch.h>
33
34#include "schizo_regs.h"
35#include "safari_interface.h"
36
37#include "schizo_stc.h"
38#include "schizo_mdu.h"
39#include "schizo_iommu.h"
40#include "decl_macros.h"
41
42extern int debug_ctr;
43
44#define BUS(n) ((n) << 16)
45
46#define MAX_INTR_DEVICES 64
47#define MAX_SLAVES 64
48
49#define PCI_A_IDX (0)
50#define PCI_B_IDX (1)
51
52#define PCI_BUS_NUM(a) (((a) & 0xf0000) >> 16)
53#define PCI_DEVICE(a) (((a) & 0xf800) >> 11)
54#define PCI_FUNCTION(a) (((a) & 0x0700) >> 8)
55
56#define PCI_CONFIG_OFFSET(a) ((a) & 0xff)
57
58
59typedef enum { memory, io, config } space_t;
60typedef enum { A, B } pbm_t;
61typedef enum Address_cycle { sac, dac } Address_cycle;
62typedef enum Xlate_mode { bypass, passthro, transltn } Xlate_mode;
63
64#define Mem_Timing1_CTL 0x00
65#define Mem_Timing2_CTL 0x08
66#define Mem_Addr_Decode_0 0x10
67#define Mem_Addr_Decode_1 0x18
68#define Mem_Addr_Decode_2 0x20
69#define Mem_Addr_Decode_3 0x28
70#define Mem_Addr_CTL 0x30
71#define Mem_Timing3_CTL 0x38
72#define Mem_Timing4_CTL 0x40
73#define FLUSH_FLAG 0x00000001
74
75typedef struct Tlb_entry {
76 union u_tlb_tag tag;
77 union u_iotlb_data data;
78} Tlb_entry_t;
79
80typedef struct schizo_struct {
81 int mid; /* module id */
82
83 Tlb_entry_t *a_entries;
84 Tlb_entry_t *a_current_entry;
85 Tlb_entry_t *b_entries;
86 Tlb_entry_t *b_current_entry;
87
88 mutex_t lock; /* for multiple device interrupts */
89 mutex_t counter_lock; /* for multiple interrupts per device */
90 mutex_t iommu_a_lock; /* for multiple iommu/tlb updates */
91 mutex_t iommu_b_lock; /* for multiple iommu/tlb updates */
92
93 uint32_t dev_type; // Interrupt tracing
94 uint32_t dev_id; // stuff
95
96 /*Safari interface Registers */
97 /* Address Match Registers */
98
99 /**** DUMP starts from here *****/
100
101 FLDDECL(union u_safari_dev_id, safari_dev_id,, dump,);
102 FLDDECL(union u_Addr_Match_Reg, UPA0Base_addr_match,, dump,);
103 FLDDECL(union u_Addr_Match_Reg, UPA1Base_addr_match,, dump,);
104 FLDDECL(union u_NewLinkBase_addr_match, NewLinkBase_addr_match,,
105 dump,);
106 FLDDECL(union u_NewLinkAltBase_addr_match,
107 NewLinkAltBase_addr_match,, dump,);
108 FLDDECL(union u_Addr_Match_Reg, PCI_A_MemBase_addr_match,, dump,);
109 FLDDECL(union u_PCI_A_ConfigBase_addr_match,
110 PCI_A_ConfigBase_addr_match,, dump,);
111 FLDDECL(union u_Addr_Match_Reg, PCI_B_MemBase_addr_match,, dump,);
112 FLDDECL(union u_PCI_B_ConfigBase_addr_match,
113 PCI_B_ConfigBase_addr_match,, dump,);
114
115 /*Address Mask Registers */
116 union u_Addr_Mask_Reg UPA0Base_addr_mask;
117 union u_Addr_Mask_Reg UPA1Base_addr_mask;
118 FLDDECL(union u_NewLinkBase_addr_mask, NewLinkBase_addr_mask,,
119 dump,);
120 FLDDECL(union u_NewLinkAltBase_addr_mask, NewLinkAltBase_addr_mask,,
121 dump,);
122 FLDDECL(union u_Addr_Mask_Reg, PCI_A_MemBase_addr_mask,, dump,);
123 FLDDECL(union u_PCI_A_ConfigBase_addr_mask,
124 PCI_A_ConfigBase_addr_mask,, dump,);
125 FLDDECL(union u_Addr_Mask_Reg, PCI_B_MemBase_addr_mask,, dump,);
126 FLDDECL(union u_PCI_B_ConfigBase_addr_mask,
127 PCI_B_ConfigBase_addr_mask,, dump,);
128
129
130 FLDDECL(union u_schizo_cntrl, schizo_cntrl,, dump,); /* may change to schizo */
131 FLDDECL(union u_upa_port_id, upa_port_id,, dump,);
132 FLDDECL(union u_upa_config, upa_config,, dump,);
133
134 FLDDECL(union u_ecc_cntrl, ecc_cntrl,, dump,);
135 FLDDECL(union u_ue_afsr, ue_afsr,, dump,);
136 FLDDECL(union u_ue_afar, ue_afar,, dump,);
137 FLDDECL(union u_ce_afsr, ce_afsr,, dump,);
138 FLDDECL(union u_ce_afar, ce_afar,, dump,);
139
140 FLDDECL(union u_ffb_config_register, ffb_config_reg,[2], dump,);
141
142 FLDDECL(union u_pci_bus_cntrl, pci_bus_a_cntrl,, dump,);
143 FLDDECL(union u_pci_bus_afsr, pci_bus_a_afsr,, dump,);
144 FLDDECL(union u_pci_bus_afar, pci_bus_a_afar,, dump,);
145 FLDDECL(union u_pci_bus_cntrl, pci_bus_b_cntrl,, dump,);
146 FLDDECL(union u_pci_bus_afsr, pci_bus_b_afsr,, dump,);
147 FLDDECL(union u_pci_bus_afar, pci_bus_b_afar,, dump,);
148 FLDDECL(union u_perf_counter, perf_counter,, dump,);
149 FLDDECL(union u_perf_monitor, perf_monitor,, dump,);
150
151 /* stc regs */
152
153 FLDDECL(union u_stc_cntrl, stc_a_cntrl,, dump,);
154 FLDDECL(union u_stc_cntrl, stc_b_cntrl,, dump,);
155 FLDDECL(union u_stc_flush, stc_a_flush,, dump,);
156 FLDDECL(union u_stc_flush, stc_b_flush,, dump,);
157 FLDDECL(union u_stc_flsync, stc_a_flsync,, dump,);
158 FLDDECL(union u_stc_flsync, stc_b_flsync,, dump,);
159
160 /* FIXME! how to deal with this in genMemberUtils? */
161 FLDDECL(union u_stc_data_diag, stc_data_diag_a,
162 [NUM_STC_ENTRIES][LWORDS_PER_ENTRY], dump,);
163 FLDDECL(union u_stc_ptag_diag, stc_ptag_diag_a,[NUM_STC_ENTRIES],
164 dump,);
165 FLDDECL(union u_stc_ltag_diag, stc_ltag_diag_a,[NUM_STC_ENTRIES],
166 dump,);
167 FLDDECL(union u_stc_cntx_mtch_diag, stc_cntx_mtch_diag_a,, dump,);
168 /* FIXME! how to deal with this in genMemberUtils? */
169 FLDDECL(union u_stc_error_diag, stc_error_diag_a,
170 [NUM_STC_ENTRIES][LWORDS_PER_ENTRY], dump,);
171 /* FIXME! how to deal with this in genMemberUtils? */
172 FLDDECL(union u_stc_data_diag, stc_data_diag_b,
173 [NUM_STC_ENTRIES][LWORDS_PER_ENTRY], dump,);
174 FLDDECL(union u_stc_ptag_diag, stc_ptag_diag_b,[NUM_STC_ENTRIES],
175 dump,);
176 FLDDECL(union u_stc_ltag_diag, stc_ltag_diag_b,[NUM_STC_ENTRIES],
177 dump,);
178 FLDDECL(union u_stc_cntx_mtch_diag, stc_cntx_mtch_diag_b,, dump,);
179 /* FIXME! how to deal with this in genMemberUtils? */
180 FLDDECL(union u_stc_error_diag, stc_error_diag_b,
181 [NUM_STC_ENTRIES][LWORDS_PER_ENTRY], dump,);
182
183 /* IOMMU A */
184 FLDDECL(int, a_num_entries,, dump,);
185 FLDDECL(union u_iommu_cntrl_reg, a_iommu_cntrl,, dump,);
186 FLDDECL(union u_flush_page_reg, a_flush_page,, dump,);
187 FLDDECL(union u_flush_context_reg, a_flush_context,, dump,);
188 FLDDECL(union u_imtbr, a_imtbr,, dump,);
189 FLDDECL(int, a_lru_entry_num,, dump,);
190 FLDDECL(int, a_shift_reg,[16], dump,);
191 FLDDECL(union u_pcibus_va_diag, a_pcibus_va_diag,, dump,);
192 FLDDECL(union u_tag_cmpr_diag, a_tag_cmpr_diag,, dump,);
193 FLDDECL(union u_lru_q_diag, a_lru_q_diag,[16], dump,);
194
195 /* IOMMU B */
196 FLDDECL(int, b_num_entries,, dump,);
197 FLDDECL(union u_iommu_cntrl_reg, b_iommu_cntrl,, dump,);
198 FLDDECL(union u_flush_page_reg, b_flush_page,, dump,);
199 FLDDECL(union u_flush_context_reg, b_flush_context,, dump,);
200 FLDDECL(union u_imtbr, b_imtbr,, dump,);
201 FLDDECL(int, b_lru_entry_num,, dump,);
202 FLDDECL(int, b_shift_reg,[16], dump,);
203 FLDDECL(union u_pcibus_va_diag, b_pcibus_va_diag,, dump,);
204 FLDDECL(union u_tag_cmpr_diag, b_tag_cmpr_diag,, dump,);
205 FLDDECL(union u_lru_q_diag, b_lru_q_diag,[16], dump,);
206
207
208 /* Mondo Stuff */
209 FLDDECL(bool_t, pending_intr,, dump,);
210 FLDDECL(union u_int_mapping, intr_map_reg,[64], dump,);
211 FLDDECL(union u_clear_int, clr_int_reg,[64], dump,);
212 FLDDECL(int, pending_intr_counter,[64], dump,);
213
214 FLDDECL (union u_int_mapping, upa_slot0_intr_map_reg,[2], dump,);
215 FLDDECL (union u_int_mapping, upa_slot1_intr_map_reg,[2], dump,);
216
217
218 FLDDECL(union u_int_retry_timer, retry_timer,, dump,);
219
220 // FIXME: There should be TWO obio_isr and TWO pci_isr because of
221 // PCI A & B
222
223 FLDDECL(union u_obio_isr, obio_isr,, dump,);
224 FLDDECL(union u_pci_isr, pci_isr,, dump,);
225
226 FLDDECL(union u_pci_bus_diag, pci_bus_a_diag,, dump,);
227 FLDDECL(union u_pci_bus_diag, pci_bus_b_diag,, dump,);
228
229 FLDDECL(uint64_t, SafariBase,, dump,);
230 FLDDECL(uint64_t, FCode,, dump,);
231 FLDDECL(uint64_t, SafariCSRBase,, dump,);
232 FLDDECL(uint64_t, NewLinkCSRBase,, dump,);
233 FLDDECL(uint64_t, SafariErrorBase,, dump,);
234 FLDDECL(uint64_t, PCI_A_CSRBase,, dump,);
235 FLDDECL(uint64_t, PCI_A_IOBase,, dump,);
236 FLDDECL(uint64_t, PCI_B_CSRBase,, dump,);
237 FLDDECL(uint64_t, PCI_B_IOBase,, dump,);
238
239 FLDDECL(uint64_t, PBM_B_CONFIG_PADDR,, dump,);
240 FLDDECL(uint64_t, PBM_B_IO_PADDR,, dump,);
241 FLDDECL(uint64_t, PBM_A_CONFIG_PADDR,, dump,);
242 FLDDECL(uint64_t, PBM_A_IO_PADDR,, dump,);
243 FLDDECL(uint64_t, PBM_A_MEM_PADDR,, dump,);
244 FLDDECL(uint64_t, PBM_B_MEM_PADDR,, dump,);
245} schizo_structT;
246
247/////////////////////////////////////////////////////////////////
248// SCHIZO extensions (IO ld/st extension implementation
249/////////////////////////////////////////////////////////////////
250
251int
252schizo_ext_process (uint32_t cpu_id, uint64_t paddr, bool_t wr, uint32_t size, uint64_t* buf);
253
254
255typedef uint8_t (*schizo_ld_ext_handler_t) (void *cd, struct BlzMemop *);
256typedef uint8_t (*schizo_st_ext_handler_t) (void *cd, struct BlzMemop *);
257
258typedef int (*schizo_ld_mmi_handler_t) (void *cd, uint64_t paddr, uint64_t *buf, int size, void *cpu);
259typedef int (*schizo_st_mmi_handler_t) (void *cd, uint64_t paddr, uint64_t *buf, int size, void *cpu);
260
261
262typedef struct schizo_ext
263{
264 uint64_t start_addr,
265 end_addr,
266 range;
267
268 schizo_ld_ext_handler_t schizo_ld_handler;
269 schizo_st_ext_handler_t schizo_st_handler;
270 schizo_ld_mmi_handler_t schizo_ld_mmi_handler;
271 schizo_st_mmi_handler_t schizo_st_mmi_handler;
272
273 // TODO : interrupts ??
274
275 struct schizo_ext *next;
276} schizo_ext_t;
277
278
279#define NI_ROM_SIZE 0x40000 // ???
280#define NI_ROM_ADDR 0xfff0000000LLU // ???
281#define NI_CONS_ADDR 0xEF00000000LLU
282#define NI_CONS_SIZE 0x2000LLU
283
284#ifdef NIAGARA
285
286typedef struct ni_rom
287{
288
289 uint64_t start_addr;
290 uint64_t end_addr;
291 uint64_t size;
292 uint8_t *ptr_rom;
293
294} ni_rom_t;
295
296void init_schizo_console (uint64_t ba, uint64_t ea);
297
298#endif
299
300void
301schizo_ext_init (uint64_t addr, uint64_t size);
302
303bool_t
304schizo_rom_load (uint32_t cpu_id, uint64_t paddr, uint32_t size, uint64_t *buf);
305
306bool_t
307schizo_rom_store (uint32_t cpu_id, uint64_t paddr, uint32_t size, uint64_t *buf);
308
309bool_t
310schizo_rom_match (uint64_t paddr) ;
311
312///////////////////////////////////////////////
313//
314// Schizo PROPS impl
315//
316
317typedef enum {
318
319 DEV_SCSI = 11,
320 DEV_ETHERNET = 22,
321 DEV_SERIAL = 33
322
323} DevType;
324
325
326void * schizo_add_dev_to_conf ( uint32_t type);
327void schizo_add_int_dev_props (void *vpv , char *props_name, uint64_t value);
328
329#endif /* _SCHIZO_IMPL_H */
330
331
332
333
334
335
336
337
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.