[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / serial / include / serial_common.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: serial_common.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright (C) 1991, Sun Microsystems, Inc.
 */
#ident       "@(#)1.3 05/05/11 SMI serial_common.h"

/*
 * Uart registers:
 *
 * There are 16 write registers and 9 read registers in each channel.
 * As usual, the two channels are ALMOST orthogonal, not exactly.
 * Most regs can only be written to, or read, but not both.
 * To access one, you must first write to register 0 with the number of
 * the register you are interested in, then read/write the actual value.
 */

/* bits in RR0 -- Xmit/Rcv Buffer Status & External Status */
#define	RR0			0x00
#define	RX_CHAR_AVAILABLE	0x01	/* received character available */
#define	TX_READY		0x04	/* Tx Buffer Empty */
#define	DCD			0x08	/* Data Carrier Detect */
#define	CTS			0x20	/* Clear To Send */

/* bits in RR1 -- Special Rcv Condition status */
#define	ALL_SENT	0x01	/* All characters Sent */

/*
 * bits in R/WR2 -- interrupt vector number
 *
 * NOTE that RR2 in channel A is unmodified, while in channel B it is
 * modified by the current status of the UARTs.  (This is independent
 * of the setting of WR9_VIS.)  If no interrupts are pending, the modified
 * status is Channel B Special Receive.  It can be written from
 * either channel.  Vector Includes Status (VIS) codes:
 * (these codes get placed in channel B's RR2 on interrupt conditions
 * if WR9.VIS is set)
 */
#define	VIS_LO_MASK	0x0e	/* VIS low bits V3,V2,V1 */
#define	VIS_HI_MASK	0x70	/* VIS hi  bits V6,V5,V4 */
#define TX_BUF_EMPTY	0x00	/* transmit buffer empty */
#define XS_CHANGE	0x02	/* external/status change */
#define	RX_CHAR_AVAIL	0x04	/* receive character available */
#define	SRC		0x06	/* special receive condition */
#define	CHAN_B		0x00	/* channel/port b */
#define	CHAN_A		0x08	/* channel/port a */

/*
 * bits in RR3 -- Interrupt Pending flags for both channels
 *
 * The status for both channels are reported in channel A
 * (this register only exists in channel A; this register can only
 * be read from channel A)
 */
#define	B_IP_MASK	0x07	/* channel B IP bit mask */
#define	A_IP_MASK	0x38	/* channel A IP bit mask */
#define	B_XS_IP		0x01	/* channel B External/Status Int Pending */
#define	B_TX_IP		0x02	/* channel B Transmit Int Pending */
#define	B_RX_IP		0x04	/* channel B Receive Int Pending */
#define	A_XS_IP		0x08	/* channel A External/Status Int Pending */
#define	A_TX_IP		0x10	/* channel A Transmit Int Pending */
#define	A_RX_IP		0x20	/* channel A Receive Intr Pending */

/* bits in RR8 -- this is the same as reading the Data port */

/* bits in R/WR12 -- lower byte of time constant for baud rate generator */

/* bits in R/WR13 -- upper byte of time constant for baud rate generator */

/* bits in R/WR15 -- interrupt enables for status conditions */

/* bits in WR0 -- common commands and register pointers */
#define	REG_NUMBER	0x07
#define	POINT_HIGH	0x08
#define	WR0_BITS3_5	0x38	/* wr0 bits 3 through 5       */
#define	WR0_BITS4_5	0x30	/* wr0 bits 4 through 5       */
#define	WR0_BITS0_4	0xe0	/* Clear WR0 bits 0 through 4 */

#define REGS_0_3	0x03
#define REG_2		0x02
#define	REG_3		0x03

#define	CRC_MASK	0xc0
#define	CMDCODE_MASK	0x38
#define	REG_MASK	0x03

#define	RESET_XS_INT	0x10	/* reset Ext/Stat interrupts */
#define	RESET_TX_INT	0x28	/* reset TxINT Pending */
#define ENABLE_RX_INT	0x20	/* enable INT on next Rx character */
#define RESET_ERROR	0x30	/* error reset */
#define RESET_IUS	0x38	/* reset highest Interrupt Under Service */

/* bits in WR1 -- Tx/Rx Interrupt & data tranfer mode register */
#define	XS_INT_ENABLED	0x01	/* External/Status Master Interrupt Enable */
#define	Tx_INT_ENABLED	0x02	/* Transmit Interrupt Enabled */
#define	Rx_INT_ENABLED	0x18	/* Receive Interrupt Enabled     */
#define	Rx_INT_ALL_d4	0x10	/* Int on all Rx chars (bit d4)  */
#define	Rx_INT_ALL_d3	0xf7	/* Int on all Rx chars (bit d3)  */

/* bits in WR2 -- are defined above as R/WR2. */

/* bits in WR5 -- transmit parameter & controls */
#define	RTS		0x02	/* Request To Send */
#define	DTR		0x80	/* Data Terminal Ready */

/*
 * bits in WR9 -- master interrupt control and reset.
 * Accessible thru either channel, there's only one of them.
 */
#define	VIS		0x01	/* vector includes status */
#define	MIE		0x08	/* master interrupt enable */


/*--------------------------------------------------------------------
 * #defines for register manipulation
 *--------------------------------------------------------------------
 */

/* Receive interrupt enabled ? */
#define RCV_INT_ENABLED(msp, portnum) \
            (msp->scc.port[portnum].wr[1] & Rx_INT_ENABLED ? 1 : 0)

#define SET_RCV_INT_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[1] = \
            (msp->scc.port[portnum].wr[1] | Rx_INT_ALL_d4) & Rx_INT_ALL_d3)

/* Transmit interrupt enabled ? */
#define TX_INT_ENABLED(msp, portnum) \
            (msp->scc.port[portnum].wr[1] & Tx_INT_ENABLED ? 1 : 0)

/* Master Interrupt Enabled ? */
#define INTERRUPTS_ENABLED(msp, portnum) \
		(msp->scc.port[portnum].wr[9] & MIE ? 1 : 0)

#define SET_INTERRUPTS_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[9] |= MIE)

#define CLEAR_INTERRUPTS_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[9] &= ~MIE)

/*
 * Vector Include Status kept on RR2 Channel B only 
 */
#define SET_VIS_RX_CHAR_AVAIL(msp,portnum) \
	    ( msp->scc.port[PORT_B].rr[2] |= ((portnum == PORT_A) ? \
		(CHAN_A | RX_CHAR_AVAIL) : (CHAN_B | RX_CHAR_AVAIL)) )
#define CLEAR_VIS_RX_CHAR_AVAIL(msp) (msp->scc.port[PORT_B].rr[2] &= ~RX_CHAR_AVAIL)

#define SET_VIS_TX_BUF_EMPTY(msp,portnum) \
	    ( msp->scc.port[PORT_B].rr[2] |= ((portnum == PORT_A) ? \
		(CHAN_A | TX_BUF_EMPTY) : (CHAN_B | TX_BUF_EMPTY)) )

#define SET_VIS_XS_CHANGE(msp,portnum) \
	    ( msp->scc.port[PORT_B].rr[2] |= ((portnum == PORT_A) ? \
		(CHAN_A | XS_CHANGE) : (CHAN_B | XS_CHANGE)) )
#define CLEAR_VIS_XS_CHANGE(msp) \
	    ( msp->scc.port[PORT_B].rr[2] &= ~XS_CHANGE )

/*
 * Interrupt status kept on RR3 Channel A only 
 */
/* Rcv Interrupt Pending set? */
#define RCV_INT_PENDING(msp, portnum) \
    ( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_RX_IP : B_RX_IP)) \
       ? 1 : 0)
#define SET_RCV_INT_PENDING(msp, portnum) \
    ( msp->scc.port[PORT_A].rr[3] |= ((portnum == PORT_A) ? A_RX_IP : B_RX_IP) )
#define CLEAR_RCV_INT_PENDING(msp, portnum) \
    (msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_RX_IP : ~B_RX_IP))

/* Tx Interrupt Pending set? */
#define TX_INT_PENDING(msp, portnum) \
    ( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_TX_IP : B_TX_IP)) \
       ? 1 : 0)
#define SET_TX_INT_PENDING(msp, portnum) \
    ( msp->scc.port[PORT_A].rr[3] |= ((portnum == PORT_A) ? A_TX_IP : B_TX_IP) )

#define CLEAR_TX_INT_PENDING(msp, portnum) \
    (msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_TX_IP : ~B_TX_IP))

/* Ext/Status Interrupt Pending set? */
#define XS_INT_PENDING(msp, portnum) \
    ( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_XS_IP : B_XS_IP)) \
       ? 1 : 0)
#define SET_XS_INT_PENDING(msp, portnum) \
    ( msp->scc.port[PORT_A].rr[3] |= ((portnum == PORT_A) ? A_XS_IP : B_XS_IP) )
#define CLEAR_XS_INT_PENDING(msp, portnum) \
    (msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_XS_IP : ~B_XS_IP))

// FlexConfig related additions
typedef int (*serial_reg_acc)(void *, char *buf, uint64_t paddr, bool_t wr);
typedef void (*serial_send)(void *, char *, int portnum);
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: serial_common.h
	5	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	7	*
	8	* The above named program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public
	10	* License version 2 as published by the Free Software Foundation.
	11	*
	12	* The above named program is distributed in the hope that it will be
	13	* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public
	18	* License along with this work; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*
	21	* ========== Copyright Header End ============================================
	22	*/
	23	/*
	24	* Copyright (C) 1991, Sun Microsystems, Inc.
	25	*/
	26	#ident "@(#)1.3 05/05/11 SMI serial_common.h"
	27
	28	/*
	29	* Uart registers:
	30	*
	31	* There are 16 write registers and 9 read registers in each channel.
	32	* As usual, the two channels are ALMOST orthogonal, not exactly.
	33	* Most regs can only be written to, or read, but not both.
	34	* To access one, you must first write to register 0 with the number of
	35	* the register you are interested in, then read/write the actual value.
	36	*/
	37
	38	/* bits in RR0 -- Xmit/Rcv Buffer Status & External Status */
	39	#define RR0 0x00
	40	#define RX_CHAR_AVAILABLE 0x01 /* received character available */
	41	#define TX_READY 0x04 /* Tx Buffer Empty */
	42	#define DCD 0x08 /* Data Carrier Detect */
	43	#define CTS 0x20 /* Clear To Send */
	44
	45	/* bits in RR1 -- Special Rcv Condition status */
	46	#define ALL_SENT 0x01 /* All characters Sent */
	47
	48	/*
	49	* bits in R/WR2 -- interrupt vector number
	50	*
	51	* NOTE that RR2 in channel A is unmodified, while in channel B it is
	52	* modified by the current status of the UARTs. (This is independent
	53	* of the setting of WR9_VIS.) If no interrupts are pending, the modified
	54	* status is Channel B Special Receive. It can be written from
	55	* either channel. Vector Includes Status (VIS) codes:
	56	* (these codes get placed in channel B's RR2 on interrupt conditions
	57	* if WR9.VIS is set)
	58	*/
	59	#define VIS_LO_MASK 0x0e /* VIS low bits V3,V2,V1 */
	60	#define VIS_HI_MASK 0x70 /* VIS hi bits V6,V5,V4 */
	61	#define TX_BUF_EMPTY 0x00 /* transmit buffer empty */
	62	#define XS_CHANGE 0x02 /* external/status change */
	63	#define RX_CHAR_AVAIL 0x04 /* receive character available */
	64	#define SRC 0x06 /* special receive condition */
65	#define CHAN_B 0x00 /* channel/port b */
66	#define CHAN_A 0x08 /* channel/port a */
67
68	/*
69	* bits in RR3 -- Interrupt Pending flags for both channels
70	*
71	* The status for both channels are reported in channel A
72	* (this register only exists in channel A; this register can only
73	* be read from channel A)
74	*/
75	#define B_IP_MASK 0x07 /* channel B IP bit mask */
76	#define A_IP_MASK 0x38 /* channel A IP bit mask */
77	#define B_XS_IP 0x01 /* channel B External/Status Int Pending */
78	#define B_TX_IP 0x02 /* channel B Transmit Int Pending */
79	#define B_RX_IP 0x04 /* channel B Receive Int Pending */
80	#define A_XS_IP 0x08 /* channel A External/Status Int Pending */
81	#define A_TX_IP 0x10 /* channel A Transmit Int Pending */
82	#define A_RX_IP 0x20 /* channel A Receive Intr Pending */
83
84	/* bits in RR8 -- this is the same as reading the Data port */
85
86	/* bits in R/WR12 -- lower byte of time constant for baud rate generator */
87
88	/* bits in R/WR13 -- upper byte of time constant for baud rate generator */
89
90	/* bits in R/WR15 -- interrupt enables for status conditions */
91
92	/* bits in WR0 -- common commands and register pointers */
93	#define REG_NUMBER 0x07
94	#define POINT_HIGH 0x08
95	#define WR0_BITS3_5 0x38 /* wr0 bits 3 through 5 */
96	#define WR0_BITS4_5 0x30 /* wr0 bits 4 through 5 */
97	#define WR0_BITS0_4 0xe0 /* Clear WR0 bits 0 through 4 */
98
99	#define REGS_0_3 0x03
100	#define REG_2 0x02
101	#define REG_3 0x03
102
103	#define CRC_MASK 0xc0
104	#define CMDCODE_MASK 0x38
105	#define REG_MASK 0x03
106
107	#define RESET_XS_INT 0x10 /* reset Ext/Stat interrupts */
108	#define RESET_TX_INT 0x28 /* reset TxINT Pending */
109	#define ENABLE_RX_INT 0x20 /* enable INT on next Rx character */
110	#define RESET_ERROR 0x30 /* error reset */
111	#define RESET_IUS 0x38 /* reset highest Interrupt Under Service */
112
113	/* bits in WR1 -- Tx/Rx Interrupt & data tranfer mode register */
114	#define XS_INT_ENABLED 0x01 /* External/Status Master Interrupt Enable */
115	#define Tx_INT_ENABLED 0x02 /* Transmit Interrupt Enabled */
116	#define Rx_INT_ENABLED 0x18 /* Receive Interrupt Enabled */
117	#define Rx_INT_ALL_d4 0x10 /* Int on all Rx chars (bit d4) */
118	#define Rx_INT_ALL_d3 0xf7 /* Int on all Rx chars (bit d3) */
119
120	/* bits in WR2 -- are defined above as R/WR2. */
121
122	/* bits in WR5 -- transmit parameter & controls */
123	#define RTS 0x02 /* Request To Send */
124	#define DTR 0x80 /* Data Terminal Ready */
125
126	/*
127	* bits in WR9 -- master interrupt control and reset.
128	* Accessible thru either channel, there's only one of them.
129	*/
130	#define VIS 0x01 /* vector includes status */
131	#define MIE 0x08 /* master interrupt enable */
132
133
134	/*--------------------------------------------------------------------
135	* #defines for register manipulation
136	*--------------------------------------------------------------------
137	*/
138
139	/* Receive interrupt enabled ? */
140	#define RCV_INT_ENABLED(msp, portnum) \
141	(msp->scc.port[portnum].wr[1] & Rx_INT_ENABLED ? 1 : 0)
142
143	#define SET_RCV_INT_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[1] = \
144	(msp->scc.port[portnum].wr[1] \| Rx_INT_ALL_d4) & Rx_INT_ALL_d3)
145
146	/* Transmit interrupt enabled ? */
147	#define TX_INT_ENABLED(msp, portnum) \
148	(msp->scc.port[portnum].wr[1] & Tx_INT_ENABLED ? 1 : 0)
149
150	/* Master Interrupt Enabled ? */
151	#define INTERRUPTS_ENABLED(msp, portnum) \
152	(msp->scc.port[portnum].wr[9] & MIE ? 1 : 0)
153
154	#define SET_INTERRUPTS_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[9] \|= MIE)
155
156	#define CLEAR_INTERRUPTS_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[9] &= ~MIE)
157
158	/*
159	* Vector Include Status kept on RR2 Channel B only
160	*/
161	#define SET_VIS_RX_CHAR_AVAIL(msp,portnum) \
162	( msp->scc.port[PORT_B].rr[2] \|= ((portnum == PORT_A) ? \
163	(CHAN_A \| RX_CHAR_AVAIL) : (CHAN_B \| RX_CHAR_AVAIL)) )
164	#define CLEAR_VIS_RX_CHAR_AVAIL(msp) (msp->scc.port[PORT_B].rr[2] &= ~RX_CHAR_AVAIL)
165
166	#define SET_VIS_TX_BUF_EMPTY(msp,portnum) \
167	( msp->scc.port[PORT_B].rr[2] \|= ((portnum == PORT_A) ? \
168	(CHAN_A \| TX_BUF_EMPTY) : (CHAN_B \| TX_BUF_EMPTY)) )
169
170	#define SET_VIS_XS_CHANGE(msp,portnum) \
171	( msp->scc.port[PORT_B].rr[2] \|= ((portnum == PORT_A) ? \
172	(CHAN_A \| XS_CHANGE) : (CHAN_B \| XS_CHANGE)) )
173	#define CLEAR_VIS_XS_CHANGE(msp) \
174	( msp->scc.port[PORT_B].rr[2] &= ~XS_CHANGE )
175
176	/*
177	* Interrupt status kept on RR3 Channel A only
178	*/
179	/* Rcv Interrupt Pending set? */
180	#define RCV_INT_PENDING(msp, portnum) \
181	( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_RX_IP : B_RX_IP)) \
182	? 1 : 0)
183	#define SET_RCV_INT_PENDING(msp, portnum) \
184	( msp->scc.port[PORT_A].rr[3] \|= ((portnum == PORT_A) ? A_RX_IP : B_RX_IP) )
185	#define CLEAR_RCV_INT_PENDING(msp, portnum) \
186	(msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_RX_IP : ~B_RX_IP))
187
188	/* Tx Interrupt Pending set? */
189	#define TX_INT_PENDING(msp, portnum) \
190	( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_TX_IP : B_TX_IP)) \
191	? 1 : 0)
192	#define SET_TX_INT_PENDING(msp, portnum) \
193	( msp->scc.port[PORT_A].rr[3] \|= ((portnum == PORT_A) ? A_TX_IP : B_TX_IP) )
194
195	#define CLEAR_TX_INT_PENDING(msp, portnum) \
196	(msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_TX_IP : ~B_TX_IP))
197
198	/* Ext/Status Interrupt Pending set? */
199	#define XS_INT_PENDING(msp, portnum) \
200	( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_XS_IP : B_XS_IP)) \
201	? 1 : 0)
202	#define SET_XS_INT_PENDING(msp, portnum) \
203	( msp->scc.port[PORT_A].rr[3] \|= ((portnum == PORT_A) ? A_XS_IP : B_XS_IP) )
204	#define CLEAR_XS_INT_PENDING(msp, portnum) \
205	(msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_XS_IP : ~B_XS_IP))
206
207	// FlexConfig related additions
208	typedef int (serial_reg_acc)(void , char *buf, uint64_t paddr, bool_t wr);
209	typedef void (serial_send)(void , char *, int portnum);