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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / include / dev_props.h
CommitLineData
920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: dev_props.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23
24/*
25 * Copyright (c) 1992,1993,2000 by Sun Microsystems, Inc
26 */
27
28#ifndef _DEVPROPS_H
29#define _DEVPROPS_H
30
31#include <sys/pci.h>
32#include "property.h"
33
34typedef unsigned long long cell_t;
35
36typedef int ihandle_t;
37typedef void *phandle_t;
38typedef void *dnode_t;
39
40
41#define STDIN_DEV (ihandle_t)1
42#define STDOUT_DEV (ihandle_t)2
43#define MAXMLIST 150
44#define NUMMLIST 4
45#define MAXTLIST 1024
46
47/* will be drived in scsi.so with sysconf param*/
48#define PCIA_SCSI00_OFFSET_1 0x0000
49#define PCIA_SCSI00_OFFSET_2 0x0100
50#define PCIA_SCSI00_OFFSET_3 0x1000
51
52#define PCIA_SCSI01_OFFSET_1 0x2000
53#define PCIA_SCSI01_OFFSET_2 0x2100
54#define PCIA_SCSI01_OFFSET_3 0x3000
55
56#define SCSI_CTRL_RSIZE_1 0x00100
57#define SCSI_CTRL_RSIZE_2 0x00100
58#define SCSI_CTRL_RSIZE_3 0x01000
59#define SCSI_CTRL_RSIZE 0x02000
60
61
62
63char psname[] = "name";
64char psreg[] = "reg";
65char psexist[] = "existing";
66char psinterrupts[] = "interrupts";
67char psavail[] = "available";
68char psunit[] = "unit";
69char psrange[] = "ranges";
70char psccoher[] = "cache-coherence?";
71char pspagesize[] = "page-size";
72char psdevtype[] = "device_type";
73char psmmc[] = "memory-controller";
74char psvme[] = "vme";
75char psiommu[] = "iommu";
76char psproc[] = "processor";
77char psgraph[] = "graphics";
78char psblock[] = "block";
79char psnetwork[] = "network";
80char psaddress[] = "address";
81char psclasscode[] = "class-code";
82char psaddresscells[] = "#address-cells";
83char pssizecells[] = "#size-cells";
84char psdevicetype[] = "device_type";
85char psclockfrequency[] = "clock-frequency";
86char psmodel[] = "model";
87char pscompatible[] = "compatible";
88char psdevselspeed[] = "devsel-speed";
89char psmaxlatency[] = "max-latency";
90char psmingrant[] = "min-grant";
91char psrevisionid[] = "revision-id";
92char psdeviceid[] = "device-id";
93char psvendorid[] = "vendor-id";
94char psversion[] ="version";
95
96
97#if 0// also defined in type.h
98struct property {
99 char *name;
100 int size;
101 caddr_t value;
102};
103#endif
104
105typedef struct dev_element {
106 struct dev_element *next;
107 struct dev_element *slaves;
108 struct property *props;
109} devnode_t;
110
111struct dev_range {
112 u_int rng_cbustype; /* Child's address, hi order */
113 u_int rng_coffset; /* Child's address, lo order */
114 u_int rng_bustype; /* Parent's address, hi order */
115 u_int rng_offset; /* Parent's address, lo order */
116 u_int rng_size; /* size of space for this entry */
117};
118
119struct dev_reg64 {
120 uint_t addr_hi;
121 uint_t addr_lo;
122 uint_t size_hi;
123 uint_t size_lo;
124};
125
126struct pci_range {
127 u_int child_hi;
128 u_int child_mid;
129 u_int child_lo;
130 u_int parent_hi;
131 u_int parent_lo;
132 u_int size_hi;
133 u_int size_lo;
134};
135
136struct sun4u_prom_memlist {
137 u_longlong_t addr;
138 u_longlong_t size;
139};
140
141struct ihandleops {
142 void (* method1) (caddr_t);
143 void (* method2) (caddr_t);
144};
145
146
147
148/* root node:
149 */
150
151typedef struct idprom {
152 uint8_t id_format; /* format identifier */
153 /*
154 * The following fields are valid only in format IDFORM_1.
155 */
156 uint8_t id_machine; /* machine type */
157 uint8_t id_ether[6]; /* ethernet address */
158 int32_t id_date; /* date of manufacture */
159 uint32_t id_serial:24; /* serial number */
160 uint8_t id_xsum; /* xor checksum */
161 uint8_t id_undef[16]; /* undefined */
162 } idprom_t;
163
164idprom_t idprom = {
165
166 0x01,
167 /* The following fields are valid only in format IDFORM_1.
168 */
169 0x80, /* machine type */
170 0x08,0x00,0x20,0x00,0x00,0x00, /* ethernet address */
171 0x00000000, /* date of manufacture */
172 0x000000, /* serial number - 24bits */
173 0xa9, /* xor checksum */
174 0,0,0,0,0,0 /* undefined - 16 bytes */
175};
176
177static int cpu_tick_freq=900000000;
178static int excalibur_stick_freq=12500000;
179static unsigned long long ramsize;
180
181int size_cells = 0x2;
182
183ihandle_t stdin_dev = STDIN_DEV;
184ihandle_t stdout_dev = STDOUT_DEV;
185
186static caddr_t pci_a_address[] = { 0, 0, 0 };
187static caddr_t pci_b_address[] = { 0, 0, 0 };
188static int three = 3;
189static int two = 2;
190static int zero = 0;
191static int four = 4;
192
193#define SCHIZO_IO_SAFARI_PORTID 31
194#define SCHIZO_INTR(n) ((n) | (SCHIZO_IO_SAFARI_PORTID << 6))
195
196
197
198
199/*
200 * pcidisk node:
201 */
202
203#define BUS(n) ((n) << 16)
204#define DEV(n) ((n) << 11)
205#define FUN(n) ((n) << 8)
206
207#define CONFIG_ADDR(b,d,f) \
208 { PCI_ADDR_CONFIG|BUS(b)|DEV(d)|FUN(f), 0x0, 0x0, 0x0, 0x0 }
209
210#define MEMORY_ADDR(b,d,f,a,s) \
211 { PCI_RELOCAT_B|PCI_ADDR_MEM32|BUS(b)|DEV(d)|FUN(f), 0x0, (a), 0x0, (s) }
212
213#define MEMORY_ADDR_BOOTBUS(b,d,f,a,s) \
214 { PCI_RELOCAT_B|PCI_ADDR_MEM32|BUS(b)|DEV(d)|FUN(f)|0x10, 0x0, (a), 0x0, (s) }
215
216
217#if 0
218static int pciA_scsi00_intr = SCHIZO_INTR(0x0);
219static int pciA_scsi01_intr = SCHIZO_INTR(0x1);
220static int scsi_ctrl_clock_freq = 0x02625A00;
221static int scsi_ctrl_devsel_speed = 0x00000001;
222static int scsi_ctrl_classcode = 0x00010000;
223static int scsi_ctrl_max_latency = 0x00000040;
224static int scsi_ctrl_min_grant = 0x00000011;
225static int scsi_ctrl_revision_id = 0x00000003;
226static int scsi_ctrl_device_id = 0x0000000F;
227static int scsi_ctrl_vendor_id = 0x00001000;
228static pci_regspec_t pciA_scsi00_reg[] = {
229 CONFIG_ADDR(0, 0, 0),
230 MEMORY_ADDR(0, 0, 0, PCIA_SCSI00_OFFSET_1, SCSI_CTRL_RSIZE_1),
231 MEMORY_ADDR(0, 0, 0, PCIA_SCSI00_OFFSET_2, SCSI_CTRL_RSIZE_2),
232 MEMORY_ADDR(0, 0, 0, PCIA_SCSI00_OFFSET_3, SCSI_CTRL_RSIZE_3)
233};
234static struct property pciA_scsi00_props[] = {
235 { psname, 5, "scsi" },
236 { psinterrupts, ARRAY(pciA_scsi00_intr) },
237 { psdevicetype, 7, "scsi-2" },
238 { psclockfrequency, ARRAY(scsi_ctrl_clock_freq) },
239 { psreg, RARRAY(pciA_scsi00_reg) },
240 { psmodel, 15, "Symbios,53C875" },
241 { psaddresscells, ARRAY(three) },
242 { pssizecells, ARRAY(two) },
243 { pscompatible, 4, "glm" },
244 { psdevselspeed, ARRAY(scsi_ctrl_devsel_speed) },
245 { psclasscode, ARRAY(scsi_ctrl_classcode) },
246 { psmaxlatency, ARRAY(scsi_ctrl_max_latency) },
247 { psmingrant, ARRAY(scsi_ctrl_min_grant) },
248 { psrevisionid, ARRAY(scsi_ctrl_revision_id) },
249 { psdeviceid, ARRAY(scsi_ctrl_device_id) },
250 { psvendorid, ARRAY(scsi_ctrl_vendor_id) },
251 { NULL }
252};
253
254static pci_regspec_t pciA_scsi01_reg[] = {
255 CONFIG_ADDR(0, 1, 0),
256 MEMORY_ADDR(0, 1, 0, PCIA_SCSI01_OFFSET_1, SCSI_CTRL_RSIZE_1),
257 MEMORY_ADDR(0, 1, 0, PCIA_SCSI01_OFFSET_2, SCSI_CTRL_RSIZE_2),
258 MEMORY_ADDR(0, 1, 0, PCIA_SCSI01_OFFSET_3, SCSI_CTRL_RSIZE_3)
259};
260
261
262static struct property pciA_scsi01_props[] = {
263 { psname, 5, "scsi" },
264 { psinterrupts, ARRAY(pciA_scsi01_intr) },
265 { psdevicetype, 7, "scsi-2" },
266 { psclockfrequency, ARRAY(scsi_ctrl_clock_freq) },
267 { psreg, RARRAY(pciA_scsi01_reg) },
268 { psmodel, 15, "Symbios,53C875" },
269 { psaddresscells, ARRAY(three) },
270 { pssizecells, ARRAY(two) },
271 { pscompatible, 4, "glm" },
272 { psdevselspeed, ARRAY(scsi_ctrl_devsel_speed) },
273 { psclasscode, ARRAY(scsi_ctrl_classcode) },
274 { psmaxlatency, ARRAY(scsi_ctrl_max_latency) },
275 { psmingrant, ARRAY(scsi_ctrl_min_grant) },
276 { psrevisionid, ARRAY(scsi_ctrl_revision_id) },
277 { psdeviceid, ARRAY(scsi_ctrl_device_id) },
278 { psvendorid, ARRAY(scsi_ctrl_vendor_id) },
279 { NULL }
280};
281#endif
282
283/* bootbus controller */
284#define BOOTBUS_CTRL_OFFSET 0x90000
285#define BOOTBUS_CTRL_RSIZE 0x8000000
286
287/*
288 * bootbus controller node:
289 */
290static pci_regspec_t bootbus_ctrl_reg[] =
291 { CONFIG_ADDR(1, 4, 0),
292 MEMORY_ADDR_BOOTBUS(1, 4, 0, BOOTBUS_CTRL_OFFSET, BOOTBUS_CTRL_RSIZE)
293 };
294
295static int bootbus_ctrl_intr = SCHIZO_INTR(0x1d); //use the interrupe for diskB4
296
297static int bootbus_ctrl_classcode = 0x00068000;
298static int bootbus_ctrl_devsel_speed = 0x00000001;
299static int bootbus_ctrl_max_latency = 0x000000;
300static int bootbus_ctrl_min_grant = 0x000000;
301static int bootbus_ctrl_device_id = 0x0000c416;
302static int bootbus_ctrl_vendor_id = 0x0000108e;
303static int bootbus_ctrl_revision_id = 0x00000002;
304static int bootbus_ctrl_latency_timer = 0x40;
305static int bootbus_ctrl_cache_line_size = 0x10;
306
307static struct property bootbus_ctrl_props[] =
308 { { psname, 19, "bootbus-controller" },
309 { "model", 12, "SUNW,sgsbbc" },
310 { psreg, RARRAY(bootbus_ctrl_reg) },
311 { psinterrupts, ARRAY(bootbus_ctrl_intr) },
312 { psclasscode, ARRAY(bootbus_ctrl_classcode)},
313 { psdevselspeed, ARRAY(bootbus_ctrl_devsel_speed) },
314 { psmaxlatency, ARRAY(bootbus_ctrl_max_latency) },
315 { psmingrant, ARRAY(bootbus_ctrl_min_grant) },
316 { psrevisionid, ARRAY(bootbus_ctrl_revision_id) },
317 { "latency-timer", ARRAY(bootbus_ctrl_latency_timer) },
318 { "cache-line-size", ARRAY(bootbus_ctrl_cache_line_size)},
319 { psdeviceid, ARRAY(bootbus_ctrl_device_id) },
320 { psvendorid, ARRAY(bootbus_ctrl_vendor_id) },
321 { "compatible", 7, "sgsbbc"},
322 { NULL },
323 };
324
325devnode_t bootbus_ctrl_info = {NULL, NULL, bootbus_ctrl_props, }; // on pciB slot 4
326/*
327 * pcisimc node:
328 */
329/* pcisimc (bus b) */
330#define PCISIMC_OFFSET 0x32000
331#define PCISIMC_RSIZE 0x1000
332
333static pci_regspec_t pcisimc_reg[] =
334 { CONFIG_ADDR(1, 25, 0),
335 MEMORY_ADDR(1, 25, 0, PCISIMC_OFFSET, PCISIMC_RSIZE)
336 };
337
338static int pcisimc_intr = SCHIZO_INTR(0x36);
339
340
341static int pcisimc_classcode = 0x0;
342
343static struct property pcisimc_props[] =
344 { { psname, 8, "pcisimc" },
345 { psreg, RARRAY(pcisimc_reg) },
346 { psaddresscells, ARRAY(three) },
347 { pssizecells, ARRAY(two) },
348 { psdevtype, 7, "serial" },
349 { psinterrupts, ARRAY(pcisimc_intr) },
350 { "port-b-ignore-cd", 0, 0 },
351 { "port-a-ignore-cd", 0, 0 },
352 { psclasscode, ARRAY(pcisimc_classcode)},
353 { NULL },
354 };
355static caddr_t fp_reg = 0;
356static struct property fp_props[] = {
357 { psdevicetype, 3, "fp" },
358 { psname, 3, "fp" },
359 { psaddresscells, ARRAY(four) },
360 { pssizecells, ARRAY(zero) },
361 { psreg, ARRAY(fp_reg) },
362 { NULL }
363};
364/*
365 * disk node:
366 */
367
368static struct property ssd_disk_props[] = {
369 { psdevicetype, 6, "block" },
370 { "compatible", 3, "ssd" },
371 { psname, 5, "disk" },
372 { "lun", ARRAY(zero) },
373 { NULL }
374};
375/*
376 * rtc node:
377 */
378static uint32_t rtc_addr;
379
380static struct property rtc_props[] = {
381 { psname, 4, "rtc" },
382 { "model", 7, "ds1287" },
383 { psaddresscells, ARRAY(two) },
384 { psaddress, ARRAY(rtc_addr) },
385 { NULL },
386};
387
388/*
389 * Children of pci B
390 */
391/* ll (bus b) */
392#define LL_OFFSET 0x34000
393#define LL_RSIZE 0x2000
394
395/* bid (bus a) */
396#define BID_OFFSET 0x32000
397#define BID_RSIZE 0x2000
398
399static pci_regspec_t ll_reg[] = {
400 CONFIG_ADDR(1, 26, 0),
401 MEMORY_ADDR(1, 26, 0, LL_OFFSET, LL_RSIZE)
402};
403
404static int ll_classcode = 0x0;
405
406static struct property ll_props[] = {
407 { psname, 3, "ll" },
408 { psreg, RARRAY(ll_reg) },
409 { psaddresscells, ARRAY(three) },
410 { pssizecells, ARRAY(two) },
411 { psclasscode, ARRAY(ll_classcode)},
412 { NULL },
413};
414
415/*
416 * bid node:
417 */
418static pci_regspec_t bid_reg[] = {
419 CONFIG_ADDR(0, 25, 0),
420 MEMORY_ADDR(0, 25, 0, BID_OFFSET, BID_RSIZE)
421};
422
423static int bid_classcode = 0x0;
424
425static struct property bid_props[] = {
426 { psname, 4, "bid" },
427 { psreg, RARRAY(bid_reg) },
428 { psaddresscells, ARRAY(three) },
429 { pssizecells, ARRAY(two) },
430 { psclasscode, ARRAY(bid_classcode)},
431 { NULL },
432};
433
434/*
435 * Root
436 */
437devnode_t root_info = { NULL, NULL, NULL, };
438
439devnode_t *memory_info_p = NULL;
440devnode_t *vmemory_info_p = NULL;
441
442#endif /* _DEVPROPS_H */
443
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.