Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / include / vtracer.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: vtracer.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
////////////////////////////////////////////////////////////
//
// File: vtracer.h
//
// Copyright (C) 2005 Sun Microsystems, Inc.
// All rights reserved.
//


#ifndef _sam_vtracer_h_a73ef783_
#define _sam_vtracer_h_a73ef783_

/* vtracer.h describes the interface between SAM and the tracer */


///////////////////////////////////////////////////////
//
// Instruction information
//
// Provide infomation about the instruction been executed.
// Fields in this structure are arranged according to the 
// order in which they are used during instruction lifetime.
//
const int VCPU_MAX_DEST_REG_NUM   = 32; 
const int VCPU_MAX_MEM_ACCESS_NUM = 32; 

// bit encoding for instruction information
const uint32_t VCPU_UNKNOWN_ITYPE   = 0;
const uint32_t VCPU_LOAD_ITYPE      = 1;
const uint32_t VCPU_STORE_ITYPE     = 1<<1;
const uint32_t VCPU_IO_LOAD_ITYPE   = 1<<2; 
const uint32_t VCPU_IO_STORE_ITYPE  = 1<<3; 
const uint32_t VCPU_ASI_LOAD_ITYPE  = 1<<4; 
const uint32_t VCPU_ASI_STORE_ITYPE = 1<<5;
const uint32_t VCPU_BRANCH_ITYPE    = 1<<6;
const uint32_t VCPU_ALU_ITYPE       = 1<<7; 
const uint32_t VCPU_FP_ITYPE        = 1<<8;

// register type encoding
const uint16_t VCPU_PR_RTYPE          = 1;
const uint16_t VCPU_ASR_RTYPE         = 2;
const uint16_t VCPU_INT_RTYPE         = 3;
const uint16_t VCPU_FP_SINGLE_RTYPE   = 4;
const uint16_t VCPU_FP_DOUBLE_RTYPE   = 5;
const uint16_t VCPU_HPR_RTYPE         = 6;

// address type encoding
enum VCPU_AddrType
{
   VCPU_PADDR  = 0, 
   VCPU_RADDR  = 1, 
   VCPU_VADDR  = 2
};

struct VcpuRegType
{
       uint16_t type; 
       uint16_t id; 
};

typedef union
{
   VcpuRegType r; 
   uint32_t regtid;
} 
VCPU_RegType; 


typedef struct InstrInfo 
{
     int16_t cpuid;    
     
     uint32_t pid;     // partition id
     
     // we care about priv, global, 32/64-bit arch mask
     uint32_t pstate; 

     // only for newer processors. we care about hpriv
     uint32_t hpstate; 

     uint32_t pc_type; // virtual, physical or real
     uint8_t  immu_asi;
     uint16_t icontext;
     uint64_t pc_va;
     uint64_t npc_va; 
  
     bool ifetch_trap; // if true, expect trap record

     uint64_t pc_pa;

     uint32_t opcode;  // instruction opcode 
     uint32_t itype;   // instruction type

     // insts that update registers (incl CTI, memop)
     // the most common case is 1 or 2 registers are updated (eg i-reg and ccr)
     int      nregs;        // total number of destination regs written
     VCPU_RegType dreg[VCPU_MAX_DEST_REG_NUM];   // destination register type and index
     uint64_t dval    [VCPU_MAX_DEST_REG_NUM];   // destination reg value

     
     // if branch
     bool taken;
     bool annul; // annul delay-slot inst if true

     // if memop
     uint32_t ea_type; // virtual, physical or real
     uint8_t  dmmu_asi;
     uint16_t dcontext;

     uint64_t ea_va;
     uint64_t ea_pa; 

     bool dmmu_trap; // if true, trap record follows
 

     uint64_t ld_mem_value[VCPU_MAX_MEM_ACCESS_NUM]; 
     uint64_t st_mem_value[VCPU_MAX_MEM_ACCESS_NUM]; 
     uint64_t st_bitmask;      // store value bitmask
     uint64_t ld_bitmask;      // load value bitmask
     uint32_t ld_num;        // number of loads
     uint32_t st_num;        // number of stores

     // if any instr
     bool exception; // if true, trap record follows


} 
VCPU_Instruction;

typedef struct TrapInfo 
{
    
    int16_t cpuid;
    int tno;        // trap number
    int is_async;   // asynchronous trap

    int syscallno;	// for tt 0x108
    int intrsid;	// for tt 0x060, val from IRSR (intr source id)
    int intrino;	// for tt 0x060, val from IRDR0 (solaris ino of device)

    uint32_t pc_type; // virtual, physical or real
    uint64_t pc_va;
    uint64_t npc_va;

    int      nregs;                             // total number of destination regs written
    VCPU_RegType dreg[VCPU_MAX_DEST_REG_NUM];   // destination register type and index
    uint64_t dval    [VCPU_MAX_DEST_REG_NUM];   // destination reg value

}
VCPU_Trap; 


typedef struct TLBInfo 
{
    int16_t cpuid;

    uint8_t    demap ;    // 0 = add/replace entry ; 1=invalidate 
    uint8_t    tlb_type ; // 0:INSTR, 1:DATA 2:UNIFIED
   
    // Each TLB implementor can number the lines in the TLB arbitrarily
    // For direct-mapped TLBs, the line index is obvious
    // For a K-way TLB, we recommend having idx={0,1,..,K-1}=first set
    uint16_t    tlb_index; // TLB line index, specific to each TLB impl 

    uint8_t  tlb_no ;   // which I or D TLB ? (eg. Ch+ has 3 DTLBS)

    uint8_t format; // 0=>sun4u, 1=>sun4v

    // for sun4u, tte_tag is {pa[63:13], ctxt[12:0]}
    // for sun4v, tte_tag is pa[63:0]
    uint64_t    tte_tag;  // tag for a TTE 

    // for sun4u (ch/ch+), tte_data is as described in rstf_tte_dataT
    // v:63, size:62-61, nfo:60, ie:59, pa:42-13, l:6, cp:5, cv:4, e:3, p:2, w:1, g:0

    // for sun4v, tte_data is as described in rstf_sun4v_tte_dataT
    // v:63 nfo:62 taddr: 55-13 ie:12 e:11 cp:10 cv:9 p:8 ep:7 w:6 sz:3-0

    uint64_t    tte_data; // equal to taddr for sun4v; has flags besides paddr for sun4u

    uint8_t	is_real; // sun4v only
    uint8_t	partid; // sun4v only

    uint8_t	tte_page_size;		// 0=8Kb, 1=64Kb, ...
    uint16_t    tte_context;		// The context for virt TTE

    uint64_t pagemask() const {
	register uint64_t pgsz = 1ull << (13 + 3*tte_page_size);
	return ~(pgsz - 1);
    }

    // PA is data[42:13] in sun4u, data[55:13] in sun4v
    static const uint64_t sun4u_pa_mask = (0x3fffffffull << 13);
    static const uint64_t sun4v_pa_mask = (0x7ffffffffffull << 13);

    uint64_t va() const {
	return tte_tag & pagemask();
    }

    uint64_t pa() const {
	register uint64_t rv = tte_data & pagemask();
	if (format == 0) {
	    rv &= sun4u_pa_mask;
	} else {
	    rv &= sun4v_pa_mask;
	}

	return rv;
    }

    // flags
    int v() { return (tte_data >> 63)&1; }
    int nfo() { return (tte_data >> (format?62:60)) & 1; }
    int ie() { return (tte_data >> (format?12:59)) & 1; }
    int e() { return (tte_data >> (format?11:3)) & 1; }
    int cp() {return (tte_data >> (format?10:5)) & 1; }
    int cv() { return (tte_data >> (format?9:4)) & 1; }
    int p() { return (tte_data >> (format?8:2)) & 1; }
    int ep() { return (format? ((tte_data >> 7)&1) : (tlb_type==0)); }
    int w() { return (tte_data >> (format?6:1)) & 1; }
    int l() { return format? 0: ((tte_data >> 6) & 1); }
    int g() { return format? 0: ((tte_data >> 0) & 1); }

}
VCPU_TLB; 


typedef struct HwOpInfo 
{
    int16_t  cpuid;
 
    uint32_t op_type ; // 0 = INSTR, 1 = DATA 
    
    uint64_t addr; 
    uint64_t data[2]; 
   
}
VCPU_HwOp;

// the async trace structures (dma, string) use a union type
typedef union vtracer_async_data_u {
  enum { rtype_DMA=13, rtype_STRING=14 };
  
  struct {
    uint8_t rtype; //  == rtype_DMA
    uint8_t iswrite;
    uint16_t reserved1; // always zero
    uint32_t devid;
    int64_t nbytes;
    uint64_t pa;
  } dma;

  struct {
    uint8_t rtype; // == rtype_STRING
    char s[23]; // must be null-terminated
  } strdata;

} VCPU_AsyncData;


typedef struct vtracer_syncinfo {

  // uses same value as rstracer timesync subtypes
  enum {synctype_NIL=0, synctype_LOCAL=1, synctype_GLOBAL=2 };

  int cpuid;
  int synctype; // uses synctype enumerated values
  int data; // not used for local or global barrier sync. usable for mem sync
  int64_t syncid; // monotonically increasing id shared by all processors.
  // syncid is not guaranteed to be preserved across dump/restore
} VCPU_Sync;

class VTracer_SAM_intf {
  void dump_state();
};

// Virtual Tracer interface

/* A tracer module must NOT define a static vtracer object.  The
 * vtracer object must be created by the vtracer_init() function
 * provided by the module code and called by the simulator. Also, the
 * module must provide a function called vtracer_fini() which should
 * clean up before the module is unloaded (eg unregister ui cmds, free
 * memory etc.)
 */

class VTracer
{
public:

  virtual ~VTracer() {}

  // virtual void ui_cmd(const char * tmp_cmd, int argc, const char ** tmp_argv) = 0;

  virtual int attach(VTracer_SAM_intf * /* intf */) = 0;

  virtual int instr ( VCPU_Instruction * ) = 0;
  virtual int trap  ( VCPU_Trap * ) = 0;
  virtual int tlb   ( VCPU_TLB  * ) = 0;
  virtual int hwop  ( VCPU_HwOp * ) { return 0; }
  
  virtual int async   (VCPU_AsyncData *) = 0;

  virtual int sync  (VCPU_Sync *) = 0;
 

  // for execution-driven mode
  virtual int cycle() { return 0; }

#if 0
  // these methods are called from teh simulator into the tracer
  // with information about simulated instructions and other events
  virtual void SysConf(struct vtr_SysConf * sc);

  virtual void MachState(struct vtr_MachState * ms);

  virtual void Instr(VCPU_Instruction * ii);

  virtual void Trap(struct vtr_trapinfo * ti);

  virtual void TlbUpdate(struct vtr_tlbupdate * tu);

  virtual void Dma(struct vtr_dma * dm);

#endif
}; // class VTracer


extern "C" void * vtracer_init(const char * tmp_modname); // return value is class VTracer *
extern "C" void vtracer_fini();
#endif //  _sam_vtracer_h_a73ef783_