projects / OpenSPARC-T2-SAM / blame
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1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: asi.h | |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
| 7 | * | |
| 8 | * The above named program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public | |
| 10 | * License version 2 as published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * The above named program is distributed in the hope that it will be | |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | * General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public | |
| 18 | * License along with this work; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 20 | * | |
| 21 | * ========== Copyright Header End ============================================ | |
| 22 | */ | |
| 23 | /* | |
| 24 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
| 25 | * Use is subject to license terms. | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef _ASI_H | |
| 29 | #define _ASI_H | |
| 30 | ||
| 31 | #pragma ident "@(#)asi.h 1.8 07/05/03 SMI" | |
| 32 | ||
| 33 | /* | |
| 34 | * Niagara-family ASI definitions | |
| 35 | */ | |
| 36 | ||
| 37 | #ifdef __cplusplus | |
| 38 | extern "C" { | |
| 39 | #endif | |
| 40 | ||
| 41 | ||
| 42 | #define ASI_MEM 0x14 /* Physical address, non-L1$-allocating */ | |
| 43 | #define ASI_IO 0x15 /* Physical address, non-$able w/ side-effect */ | |
| 44 | #define ASI_BLK_AIUP 0x16 /* Block store, as if user primary */ | |
| 45 | #define ASI_BLK_AIUS 0x17 /* Block store, as if user secondary */ | |
| 46 | #define ASI_MEM_LE 0x1c /* ASI_MEM, little endian */ | |
| 47 | #define ASI_IO_LE 0x1d /* ASI_IO, little endian */ | |
| 48 | #define ASI_BLK_AIUP_LE 0x1e /* ASI_BLK_AIUP, little endian */ | |
| 49 | #define ASI_BLK_AIUS_LE 0x1f /* ASI_BLK_AIUS, little endian */ | |
| 50 | ||
| 51 | #define ASI_MMU 0x21 | |
| 52 | #define ASI_BLKINIT_AIUP 0x22 | |
| 53 | #define ASI_BLKINIT_AIUS 0x23 | |
| 54 | #define ASI_BLKINIT_AIUP_LE 0x2a | |
| 55 | #define ASI_BLKINIT_AIUS_LE 0x2b | |
| 56 | ||
| 57 | #define ASI_QUAD_LDD 0x24 /* 128-bit atomic ldda/stda */ | |
| 58 | #define ASI_QUAD_LDD_REAL 0x26 /* 128-bit atomic ldda/stda real */ | |
| 59 | #define ASI_QUAD_LDD_LE 0x2c /* 128-bit atomic ldda/stda, little endian */ | |
| 60 | ||
| 61 | #define ASI_STREAM 0x40 /* Niagara streaming extensions */ | |
| 62 | #define ASI_NIAGARA 0x42 /* BIST/LSU diag registers */ /* XXX */ | |
| 63 | ||
| 64 | #define ASI_DC_DATA 0x46 /* D$ data array diag access */ | |
| 65 | #define ASI_DC_TAG 0x47 /* D$ tag array diag access */ | |
| 66 | ||
| 67 | #define ASI_HSCRATCHPAD 0x4f /* Hypervisor scratchpad registers */ | |
| 68 | ||
| 69 | #define ASI_IMMU 0x50 /* IMMU registers */ | |
| 70 | #define ASI_ITLB_DATA_IN 0x54 /* IMMU data in register */ | |
| 71 | #define ASI_ITLB_DATA_ACC 0x55 /* IMMU data access register */ | |
| 72 | #define ASI_ITLB_TAG 0x56 /* IMMU tag read register */ | |
| 73 | #define ASI_IMMU_DEMAP 0x57 /* IMMU tlb demap */ | |
| 74 | ||
| 75 | #define ASI_DMMU 0x58 /* DMMU registers */ | |
| 76 | ||
| 77 | #define IDMMU_PARTITION_ID 0x80 /* Partition ID register */ | |
| 78 | ||
| 79 | #define ASI_DTLB_DATA_IN 0x5c /* DMMU data in register */ | |
| 80 | #define ASI_DTLB_DATA_ACC 0x5d /* DMMU data access register */ | |
| 81 | #define ASI_DTLB_TAG 0x5e /* DMMU tag read register */ | |
| 82 | #define ASI_DMMU_DEMAP 0x5f /* DMMU tlb demap */ | |
| 83 | ||
| 84 | #define ASI_TLB_INVALIDATE 0x60 /* TLB invalidate registers */ | |
| 85 | ||
| 86 | #define ASI_ICACHE_INSTR 0x66 | |
| 87 | #define ASI_ICACHE_TAG 0x67 | |
| 88 | ||
| 89 | #define ASI_INTR_RCV 0x72 /* Interrupt receive register */ | |
| 90 | #define ASI_INTR_UDB_W 0x73 /* Interrupt vector dispatch register */ | |
| 91 | #define ASI_INTR_UDB_R 0x74 /* Incoming interrupt vector register */ | |
| 92 | ||
| 93 | #define ASI_BLK_INIT_P 0xe2 /* Block initializing store, primary ctx */ | |
| 94 | #define ASI_BLK_INIT_S 0xe3 /* Block initializing store, secondary ctx */ | |
| 95 | #define ASI_BLK_INIT_P_LE 0xea /* Block initializing store, primary ctx, le */ | |
| 96 | #define XXX_ASI_BLK_INIT_S 0xeb /* Block initializing store, sec ctx, le */ | |
| 97 | ||
| 98 | #define HSCRATCH0 0x20 /* first hypervisor scratch register */ | |
| 99 | #define HSCRATCH1 0x28 /* second hypervisor scratch register */ | |
| 100 | ||
| 101 | #define ASI_MAU_CONTROL 0x80 /* MA control register */ | |
| 102 | #define ASI_MAU_MPA 0x88 /* MA memory register */ | |
| 103 | #define ASI_MAU_ADDR 0x90 /* MA module ops offsets register */ | |
| 104 | #define ASI_MAU_NP 0x98 /* MA N prime value register */ | |
| 105 | #define ASI_MAU_SYNC 0xA0 /* MA Sync register */ | |
| 106 | ||
| 107 | #ifdef __cplusplus | |
| 108 | } | |
| 109 | #endif | |
| 110 | ||
| 111 | #endif /* _ASI_H */ |