[OpenSPARC-T2-SAM] / t1_fpga / src / include / hprivregs.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: hprivregs.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _HPRIVREGS_H
#define	_HPRIVREGS_H

#pragma ident	"@(#)hprivregs.h	1.20	07/05/03 SMI"

#ifdef __cplusplus
extern "C" {
#endif


/*
 * Niagara %ver
 */
#define	VER_MASK_SHIFT		24
#define	VER_MASK_MASK		0xff
#define	VER_MASK_MAJOR_SHIFT	(VER_MASK_SHIFT + 4)
#define	VER_MASK_MAJOR_MASK	0xf

/*
 * Hardware-implemented register windows
 */
#define	NWINDOWS	8

/*
 * Number of unique interrupts per strand
 */
#define	MAXINTR		64

/*
 * Max number of Global levels
 */
#define	MAXGL		3

/*
 * hpstate:
 *
 * +-----------------------------------------------------+
 * | rsvd | ENB | rsvd | RED | rsvd | HPRIV | rsvd | TLZ |
 * +-----------------------------------------------------+
 *  63..12  11   10..6    5    4..3     2       1     0
 */

#define	HPSTATE_TLZ	0x0001
#define	HPSTATE_HPRIV	0x0004
#define	HPSTATE_RED	0x0020
#define	HPSTATE_ENB	0x0800

/*
 * htstate:
 *
 * +-----------------------------------------+
 * | rsvd |  RED | rsvd | HPRIV | rsvd | TLZ |
 * +-----------------------------------------+
 *  63..6     5    4..3     2       1     0
 */

#define	HTSTATE_TLZ	0x0001
#define	HTSTATE_HPRIV	0x0004
#define	HTSTATE_RED	0x0010
#define	HTSTATE_ENB	0x0800

/*
 * hstickpending:
 *
 * +------------+
 * | rsvd | HSP |
 * +------------+
 *  63..1    0
 */

#define	HSTICKPEND_HSP	0x1

/*
 * htba:
 *
 * +---------------------------+
 * |    TBA     | TBATL | rsvd |
 * +---------------------------+
 *     63..15      14    13..0
 */
#define	TBATL		0x4000
#define	TBATL_SHIFT	14

/*
 * TLB demap register bit definitions
 * (ASI_DMMU_DEMAP/ASI_IMMU_DEMAP)
 */
#define	TLB_R_BIT		(0x200)
#define	TLB_DEMAP_PAGE_TYPE	0x00
#define	TLB_DEMAP_CTX_TYPE	0x40
#define	TLB_DEMAP_ALL_TYPE	0x80
#define	TLB_DEMAP_PRIMARY	0x00
#define	TLB_DEMAP_SECONDARY	0x10
#define	TLB_DEMAP_NUCLEUS	0x20

/*
 * LSU Control Register
 */
#define	ASI_LSUCR	0x45
#define	LSUCR_IC	0x000000001	/* I$ enable */
#define	LSUCR_DC	0x000000002	/* D$ enable */
#define	LSUCR_IM	0x000000004	/* IMMU enable */
#define	LSUCR_DM	0x000000008	/* DMMU enable */

/*
 * Misc
 */
#define	L2_CTL_REG	0xa900000000
#define	L2CR_DIS	0x00000001	/* L2$ Disable */
#define	L2CR_DMMODE	0x00000002	/* L2$ Direct-mapped mode */
#define	L2CR_SCRUBEN	0x00000004	/* L2$ Hardware scrub enable */

/*
 * INT_VEC_DIS constants
 */
#define	INT_VEC_DIS_TYPE_SHIFT	16
#define	INT_VEC_DIS_VCID_SHIFT	8
#define	INT_VEC_DIS_TYPE_INT	0x0
#define	INT_VEC_DIS_TYPE_RESET	0x1
#define	INT_VEC_DIS_TYPE_IDLE	0x2
#define	INT_VEC_DIS_TYPE_RESUME	0x3
#define	INT_VEC_DIS_VECTOR_RESET  0x1

/* BEGIN CSTYLED */
/*
 * Interrupt Vector Dispatch Macros
 */
/*
 * INT_VEC_DSPCH_ONE - interrupt vector dispatch one target
 *
 * Sends interrupt TYPE to any strand including the executing one.
 *
 * Delay Slot: no
 */
/* BEGIN CSTYLED */
#define	INT_VEC_DSPCH_ONE(TYPE, tgt, scr1, scr2) \
	setx	IOBBASE + INT_VEC_DIS, scr1, scr2			;\
	set	(TYPE) << INT_VEC_DIS_TYPE_SHIFT, scr1			;\
	sllx	tgt, INT_VEC_DIS_VCID_SHIFT, tgt			;\
	or	scr1, tgt, scr1						;\
	stx	scr1, [scr2]
/* END CSTYLED */

/*
 * INT_VEC_DSPCH_ALL - interrupt vector dispatch all
 *
 * Sends interrupt TYPE to all strands whose bit is set in SRC, excluding
 *   the executing one. SRC and DST bitmasks are updated.
 *
 * Delay Slot: no
 */
/* BEGIN CSTYLED */
#define	INT_VEC_DSPCH_ALL(TYPE, SRC, DST, scr1, scr2) \
	.pushlocals							;\
	rd	STR_STATUS_REG, scr2		/* my ID             */	;\
	srlx	scr2, STR_STATUS_CPU_ID_SHIFT, scr2			;\
	and	scr2, STR_STATUS_CPU_ID_MASK, scr2			;\
	mov	1, scr1							;\
	sllx	scr1, scr2, scr1		/* my bit            */	;\
	ldx	[SRC], scr2			/* Source state      */	;\
	stx	scr1, [SRC]			/* new Source        */	;\
	bclr	scr1, scr2			/* clear my bit      */	;\
	ldx	[DST], scr1			/* Destination state */	;\
	bset	scr2, scr1			/* add new bits      */	;\
	stx	scr1, [DST]			/* new To            */	;\
	setx	IOBBASE + INT_VEC_DIS, scr1, DST			;\
	set	(TYPE) << INT_VEC_DIS_TYPE_SHIFT, scr1			;\
1:	btst	1, scr2				/* valid strand?     */	;\
	bnz,a,pn %xcc, 2f			/*   yes: store      */	;\
	  stx	scr1, [DST]			/*   no: annul       */	;\
2:	srlx	scr2, 1, scr2			/* next strand bit   */	;\
	brnz	scr2, 1b			/* more to do        */	;\
	  inc	1 << INT_VEC_DIS_VCID_SHIFT, scr1			;\
	.poplocals
/* END CSTYLED */

/*
 * IDLE_ALL_STRAND
 *
 * Sends interrupt IDLE to all strands whose bit is set in CONFIG_STACTIVE,
 * excluding the executing one. CONFIG_STACTIVE, CONFIG_STIDLE are
 * updated.
 *
 * Delay Slot: no
 */
/* BEGIN CSTYLED */
#define	IDLE_ALL_STRAND(strand, scr1, scr2, scr3, scr4) \
	ldx	[strand + STRAND_CONFIGP], scr1	/* ->config*/		;\
	add	scr1, CONFIG_STACTIVE, scr3	/* ->active mask */	;\
	add	scr1, CONFIG_STIDLE, scr4	/* ->idle mask   */	;\
	INT_VEC_DSPCH_ALL(INT_VEC_DIS_TYPE_IDLE, scr3, scr4, scr1, scr2)
/* END CSTYLED */

/* BEGIN CSTYLED */
#define	RESUME_ALL_STRAND(strand, scr1, scr2, scr3, scr4) \
	ldx	[strand + STRAND_CONFIGP], scr1	/* ->config*/		;\
	add	scr1, CONFIG_STIDLE, scr3	/* ->idle mask   */	;\
	add	scr1, CONFIG_STACTIVE, scr4	/* ->active mask */	;\
	INT_VEC_DSPCH_ALL(INT_VEC_DIS_TYPE_RESUME, scr3, scr4, scr1, scr2)

#define	IS_STRAND_(state, vcpup, strand, scr1, scr2) \
	mov	1, scr1				/* bit */		;\
	sllx	scr1, strand, scr1		/* 1<<strand */		;\
	VCPU2ROOT_STRUCT(vcpup, scr2)		/* ->config*/		;\
	ldx	[scr2 + state], scr2		/* state mask */	;\
	btst	scr1, scr2			/* set cc */
/* END CSTYLED */

#define	IS_STRAND_ACTIVE(cpup, strand, scr1, scr2) \
	IS_STRAND_(CONFIG_STACTIVE, cpup, strand, scr1, scr2)

#define	IS_STRAND_HALT(cpup, strand, scr1, scr2) \
	IS_STRAND_(CONFIG_STHALT, cpup, strand, scr1, scr2)

#define	IS_STRAND_IDLE(cpup, strand, scr1, scr2) \
	IS_STRAND_(CONFIG_STIDLE, cpup, strand, scr1, scr2)

/* END CSTYLED */

#ifdef __cplusplus
}
#endif

#endif /* _HPRIVREGS_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: hprivregs.h
	5	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	7	*
	8	* The above named program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public
	10	* License version 2 as published by the Free Software Foundation.
	11	*
	12	* The above named program is distributed in the hope that it will be
	13	* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public
	18	* License along with this work; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*
	21	* ========== Copyright Header End ============================================
	22	*/
	23	/*
	24	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	25	* Use is subject to license terms.
	26	*/
	27
	28	#ifndef _HPRIVREGS_H
	29	#define _HPRIVREGS_H
	30
	31	#pragma ident "@(#)hprivregs.h 1.20 07/05/03 SMI"
	32
	33	#ifdef __cplusplus
	34	extern "C" {
	35	#endif
	36
	37
	38	/*
	39	* Niagara %ver
	40	*/
	41	#define VER_MASK_SHIFT 24
	42	#define VER_MASK_MASK 0xff
	43	#define VER_MASK_MAJOR_SHIFT (VER_MASK_SHIFT + 4)
	44	#define VER_MASK_MAJOR_MASK 0xf
	45
	46	/*
	47	* Hardware-implemented register windows
	48	*/
	49	#define NWINDOWS 8
	50
	51	/*
	52	* Number of unique interrupts per strand
	53	*/
	54	#define MAXINTR 64
	55
	56	/*
	57	* Max number of Global levels
	58	*/
	59	#define MAXGL 3
	60
	61	/*
	62	* hpstate:
	63	*
	64	* +-----------------------------------------------------+
65	* \| rsvd \| ENB \| rsvd \| RED \| rsvd \| HPRIV \| rsvd \| TLZ \|
66	* +-----------------------------------------------------+
67	* 63..12 11 10..6 5 4..3 2 1 0
68	*/
69
70	#define HPSTATE_TLZ 0x0001
71	#define HPSTATE_HPRIV 0x0004
72	#define HPSTATE_RED 0x0020
73	#define HPSTATE_ENB 0x0800
74
75	/*
76	* htstate:
77	*
78	* +-----------------------------------------+
79	* \| rsvd \| RED \| rsvd \| HPRIV \| rsvd \| TLZ \|
80	* +-----------------------------------------+
81	* 63..6 5 4..3 2 1 0
82	*/
83
84	#define HTSTATE_TLZ 0x0001
85	#define HTSTATE_HPRIV 0x0004
86	#define HTSTATE_RED 0x0010
87	#define HTSTATE_ENB 0x0800
88
89	/*
90	* hstickpending:
91	*
92	* +------------+
93	* \| rsvd \| HSP \|
94	* +------------+
95	* 63..1 0
96	*/
97
98	#define HSTICKPEND_HSP 0x1
99
100	/*
101	* htba:
102	*
103	* +---------------------------+
104	* \| TBA \| TBATL \| rsvd \|
105	* +---------------------------+
106	* 63..15 14 13..0
107	*/
108	#define TBATL 0x4000
109	#define TBATL_SHIFT 14
110
111	/*
112	* TLB demap register bit definitions
113	* (ASI_DMMU_DEMAP/ASI_IMMU_DEMAP)
114	*/
115	#define TLB_R_BIT (0x200)
116	#define TLB_DEMAP_PAGE_TYPE 0x00
117	#define TLB_DEMAP_CTX_TYPE 0x40
118	#define TLB_DEMAP_ALL_TYPE 0x80
119	#define TLB_DEMAP_PRIMARY 0x00
120	#define TLB_DEMAP_SECONDARY 0x10
121	#define TLB_DEMAP_NUCLEUS 0x20
122
123	/*
124	* LSU Control Register
125	*/
126	#define ASI_LSUCR 0x45
127	#define LSUCR_IC 0x000000001 /* I$ enable */
128	#define LSUCR_DC 0x000000002 /* D$ enable */
129	#define LSUCR_IM 0x000000004 /* IMMU enable */
130	#define LSUCR_DM 0x000000008 /* DMMU enable */
131
132	/*
133	* Misc
134	*/
135	#define L2_CTL_REG 0xa900000000
136	#define L2CR_DIS 0x00000001 /* L2$ Disable */
137	#define L2CR_DMMODE 0x00000002 /* L2$ Direct-mapped mode */
138	#define L2CR_SCRUBEN 0x00000004 /* L2$ Hardware scrub enable */
139
140	/*
141	* INT_VEC_DIS constants
142	*/
143	#define INT_VEC_DIS_TYPE_SHIFT 16
144	#define INT_VEC_DIS_VCID_SHIFT 8
145	#define INT_VEC_DIS_TYPE_INT 0x0
146	#define INT_VEC_DIS_TYPE_RESET 0x1
147	#define INT_VEC_DIS_TYPE_IDLE 0x2
148	#define INT_VEC_DIS_TYPE_RESUME 0x3
149	#define INT_VEC_DIS_VECTOR_RESET 0x1
150
151	/* BEGIN CSTYLED */
152	/*
153	* Interrupt Vector Dispatch Macros
154	*/
155	/*
156	* INT_VEC_DSPCH_ONE - interrupt vector dispatch one target
157	*
158	* Sends interrupt TYPE to any strand including the executing one.
159	*
160	* Delay Slot: no
161	*/
162	/* BEGIN CSTYLED */
163	#define INT_VEC_DSPCH_ONE(TYPE, tgt, scr1, scr2) \
164	setx IOBBASE + INT_VEC_DIS, scr1, scr2 ;\
165	set (TYPE) << INT_VEC_DIS_TYPE_SHIFT, scr1 ;\
166	sllx tgt, INT_VEC_DIS_VCID_SHIFT, tgt ;\
167	or scr1, tgt, scr1 ;\
168	stx scr1, [scr2]
169	/* END CSTYLED */
170
171	/*
172	* INT_VEC_DSPCH_ALL - interrupt vector dispatch all
173	*
174	* Sends interrupt TYPE to all strands whose bit is set in SRC, excluding
175	* the executing one. SRC and DST bitmasks are updated.
176	*
177	* Delay Slot: no
178	*/
179	/* BEGIN CSTYLED */
180	#define INT_VEC_DSPCH_ALL(TYPE, SRC, DST, scr1, scr2) \
181	.pushlocals ;\
182	rd STR_STATUS_REG, scr2 /* my ID */ ;\
183	srlx scr2, STR_STATUS_CPU_ID_SHIFT, scr2 ;\
184	and scr2, STR_STATUS_CPU_ID_MASK, scr2 ;\
185	mov 1, scr1 ;\
186	sllx scr1, scr2, scr1 /* my bit */ ;\
187	ldx [SRC], scr2 /* Source state */ ;\
188	stx scr1, [SRC] /* new Source */ ;\
189	bclr scr1, scr2 /* clear my bit */ ;\
190	ldx [DST], scr1 /* Destination state */ ;\
191	bset scr2, scr1 /* add new bits */ ;\
192	stx scr1, [DST] /* new To */ ;\
193	setx IOBBASE + INT_VEC_DIS, scr1, DST ;\
194	set (TYPE) << INT_VEC_DIS_TYPE_SHIFT, scr1 ;\
195	1: btst 1, scr2 /* valid strand? */ ;\
196	bnz,a,pn %xcc, 2f /* yes: store */ ;\
197	stx scr1, [DST] /* no: annul */ ;\
198	2: srlx scr2, 1, scr2 /* next strand bit */ ;\
199	brnz scr2, 1b /* more to do */ ;\
200	inc 1 << INT_VEC_DIS_VCID_SHIFT, scr1 ;\
201	.poplocals
202	/* END CSTYLED */
203
204	/*
205	* IDLE_ALL_STRAND
206	*
207	* Sends interrupt IDLE to all strands whose bit is set in CONFIG_STACTIVE,
208	* excluding the executing one. CONFIG_STACTIVE, CONFIG_STIDLE are
209	* updated.
210	*
211	* Delay Slot: no
212	*/
213	/* BEGIN CSTYLED */
214	#define IDLE_ALL_STRAND(strand, scr1, scr2, scr3, scr4) \
215	ldx [strand + STRAND_CONFIGP], scr1 /* ->config*/ ;\
216	add scr1, CONFIG_STACTIVE, scr3 /* ->active mask */ ;\
217	add scr1, CONFIG_STIDLE, scr4 /* ->idle mask */ ;\
218	INT_VEC_DSPCH_ALL(INT_VEC_DIS_TYPE_IDLE, scr3, scr4, scr1, scr2)
219	/* END CSTYLED */
220
221	/* BEGIN CSTYLED */
222	#define RESUME_ALL_STRAND(strand, scr1, scr2, scr3, scr4) \
223	ldx [strand + STRAND_CONFIGP], scr1 /* ->config*/ ;\
224	add scr1, CONFIG_STIDLE, scr3 /* ->idle mask */ ;\
225	add scr1, CONFIG_STACTIVE, scr4 /* ->active mask */ ;\
226	INT_VEC_DSPCH_ALL(INT_VEC_DIS_TYPE_RESUME, scr3, scr4, scr1, scr2)
227
228	#define IS_STRAND_(state, vcpup, strand, scr1, scr2) \
229	mov 1, scr1 /* bit */ ;\
230	sllx scr1, strand, scr1 /* 1<<strand */ ;\
231	VCPU2ROOT_STRUCT(vcpup, scr2) /* ->config*/ ;\
232	ldx [scr2 + state], scr2 /* state mask */ ;\
233	btst scr1, scr2 /* set cc */
234	/* END CSTYLED */
235
236	#define IS_STRAND_ACTIVE(cpup, strand, scr1, scr2) \
237	IS_STRAND_(CONFIG_STACTIVE, cpup, strand, scr1, scr2)
238
239	#define IS_STRAND_HALT(cpup, strand, scr1, scr2) \
240	IS_STRAND_(CONFIG_STHALT, cpup, strand, scr1, scr2)
241
242	#define IS_STRAND_IDLE(cpup, strand, scr1, scr2) \
243	IS_STRAND_(CONFIG_STIDLE, cpup, strand, scr1, scr2)
244
245	/* END CSTYLED */
246
247	#ifdef __cplusplus
248	}
249	#endif
250
251	#endif /* _HPRIVREGS_H */