[OpenSPARC-T2-SAM] / t1_fpga / src / include / traps.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: traps.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _SUN4V_TRAPS_H
#define	_SUN4V_TRAPS_H

#pragma ident	"@(#)traps.h	1.10	07/05/03 SMI"

#ifdef __cplusplus
extern "C" {
#endif

#define	MAXPTL			2	/* Maximum privileged trap level */
#define	MAXPGL			2	/* Maximum privileged globals level */
#define	TT_OFFSET_SHIFT		5	/* tt to trap table offset shift */
#define	TRAPTABLE_ENTRY_SIZE	(8 * 4)	/* Eight Instructions */
#define	REAL_TRAPTABLE_SIZE	(8 * TRAPTABLE_ENTRY_SIZE)
#define	TRAPTABLE_SIZE		(1 << 14)

/*
 * sun4v definition of pstate
 */
#define	PSTATE_IE		0x00000002 /* interrupt enable */
#define	PSTATE_PRIV		0x00000004 /* privilege */
#define	PSTATE_AM		0x00000008 /* address mask */
#define	PSTATE_PEF		0x00000010 /* fpu enable */
#define	PSTATE_MM_MASK		0x000000c0 /* memory model */
#define	PSTATE_MM_SHIFT		0x00000006
#define	PSTATE_TLE		0x00000100 /* trap little-endian */
#define	PSTATE_CLE		0x00000200 /* current little-endian */
#define	PSTATE_TCT		0x00001000 /* trap on control transfer */

#define	PSTATE_MM_TSO		0x00
#define	PSTATE_MM_PSO		0x40
#define	PSTATE_MM_RMO		0x80

#define	TSTATE_CWP_SHIFT	0
#define	TSTATE_CWP_MASK		0x1f
#define	TSTATE_PSTATE_SHIFT	8
#define	TSTATE_ASI_SHIFT	24
#define	TSTATE_ASI_MASK		0xff
#define	TSTATE_CCR_SHIFT	32
#define	TSTATE_GL_SHIFT		40
#define	TSTATE_GL_MASK		0x3

#define	TSTATE_PSTATE_PRIV	(PSTATE_PRIV << TSTATE_PSTATE_SHIFT)

#define	TT_GUEST_WATCHDOG	0x2	/* guest watchdog */
#define	TT_IAX			0x8	/* instruction access exception */
#define	TT_IMMU_MISS		0x9	/* instruction access MMU miss */
#define	TT_ILLINST		0x10	/* illegal instruction */
#define	TT_PRIVOP		0x11	/* privileged opcode */
#define	TT_UNIMP_LDD		0x12	/* unimplemented LDD */
#define	TT_UNIMP_STD		0x13	/* unimplemented STD */
#define	TT_FP_DISABLED		0x20	/* fp disabled */
#define	TT_FP_IEEE754		0x21	/* fp exception IEEE 754 */
#define	TT_FP_OTHER		0x22	/* fp exception other */
#define	TT_TAGOVERFLOW		0x23	/* tag overflow */
#define	TT_CLEANWIN		0x24	/* cleanwin (BIG) */
#define	TT_DIV0			0x28	/* division by zero */
#define	TT_DAX			0x30	/* data access exception */
#define	TT_DMMU_MISS		0x31	/* data access MMU miss */
#define	TT_DAP			0x33	/* data access protection */
#define	TT_ALIGN		0x34	/* mem address not aligned */
#define	TT_LDDF_ALIGN		0x35	/* LDDF mem address not aligned */
#define	TT_STDF_ALIGN		0x36	/* STDF mem address not aligned */
#define	TT_PRIVACT		0x37	/* privileged action */
#define	TT_LDQF_ALIGN		0x38	/* LDQF mem address not aligned */
#define	TT_STQF_ALIGN		0x39	/* STQF mem address not aligned */
#define	TT_INTR_LEV1		0x41	/* interrupt level 1 */
#define	TT_INTR_LEV2		0x42	/* interrupt level 2 */
#define	TT_INTR_LEV3		0x43	/* interrupt level 3 */
#define	TT_INTR_LEV4		0x44	/* interrupt level 4 */
#define	TT_INTR_LEV5		0x45	/* interrupt level 5 */
#define	TT_INTR_LEV6		0x46	/* interrupt level 6 */
#define	TT_INTR_LEV7		0x47	/* interrupt level 7 */
#define	TT_INTR_LEV8		0x48	/* interrupt level 8 */
#define	TT_INTR_LEV9		0x49	/* interrupt level 9 */
#define	TT_INTR_LEVa		0x4a	/* interrupt level a */
#define	TT_INTR_LEVb		0x4b	/* interrupt level b */
#define	TT_INTR_LEVc		0x4c	/* interrupt level c */
#define	TT_INTR_LEVd		0x4d	/* interrupt level d */
#define	TT_INTR_LEVe		0x4e	/* interrupt level e */
#define	TT_INTR_LEVf		0x4f	/* interrupt level f */
#define	TT_RA_WATCH		0x61	/* real address watchpoint */
#define	TT_VA_WATCH		0x62	/* virtual address watchpoint */
#define	TT_FAST_IMMU_MISS	0x64	/* fast immu miss (BIG) */
#define	TT_FAST_DMMU_MISS	0x68	/* fast dmmu miss (BIG) */
#define	TT_FAST_DMMU_PROT	0x6c	/* fast dmmu protection (BIG) */
#define	TT_CTI_TAKEN		0x74	/* control transfer instruction */
#define	TT_CPU_MONDO		0x7c	/* cpu mondo */
#define	TT_DEV_MONDO		0x7d	/* dev mondo */
#define	TT_RESUMABLE_ERR	0x7e	/* resumable error */
#define	TT_NONRESUMABLE_ERR	0x7f	/* non-resumable error */
#define	TT_SPILL_0_NORMAL	0x80	/* spill 0 normal (BIG) */
#define	TT_SPILL_1_NORMAL	0x84	/* spill 1 normal (BIG) */
#define	TT_SPILL_2_NORMAL	0x88	/* spill 2 normal (BIG) */
#define	TT_SPILL_3_NORMAL	0x8c	/* spill 3 normal (BIG) */
#define	TT_SPILL_4_NORMAL	0x90	/* spill 4 normal (BIG) */
#define	TT_SPILL_5_NORMAL	0x94	/* spill 5 normal (BIG) */
#define	TT_SPILL_6_NORMAL	0x98	/* spill 6 normal (BIG) */
#define	TT_SPILL_7_NORMAL	0x9c	/* spill 7 normal (BIG) */
#define	TT_SPILL_0_OTHER 	0xa0	/* spill 0 other (BIG) */
#define	TT_SPILL_1_OTHER 	0xa4	/* spill 1 other (BIG) */
#define	TT_SPILL_2_OTHER 	0xa8	/* spill 2 other (BIG) */
#define	TT_SPILL_3_OTHER 	0xac	/* spill 3 other (BIG) */
#define	TT_SPILL_4_OTHER 	0xb0	/* spill 4 other (BIG) */
#define	TT_SPILL_5_OTHER 	0xb4	/* spill 5 other (BIG) */
#define	TT_SPILL_6_OTHER 	0xb8	/* spill 6 other (BIG) */
#define	TT_SPILL_7_OTHER 	0xbc	/* spill 7 other (BIG) */
#define	TT_FILL_0_NORMAL 	0xc0	/* fill 0 normal (BIG) */
#define	TT_FILL_1_NORMAL 	0xc4	/* fill 1 normal (BIG) */
#define	TT_FILL_2_NORMAL 	0xc8	/* fill 2 normal (BIG) */
#define	TT_FILL_3_NORMAL 	0xcc	/* fill 3 normal (BIG) */
#define	TT_FILL_4_NORMAL 	0xd0	/* fill 4 normal (BIG) */
#define	TT_FILL_5_NORMAL 	0xd4	/* fill 5 normal (BIG) */
#define	TT_FILL_6_NORMAL 	0xd8	/* fill 6 normal (BIG) */
#define	TT_FILL_7_NORMAL 	0xdc	/* fill 7 normal (BIG) */
#define	TT_FILL_0_OTHER  	0xe0	/* fill 0 other (BIG) */
#define	TT_FILL_1_OTHER  	0xe4	/* fill 1 other (BIG) */
#define	TT_FILL_2_OTHER  	0xe8	/* fill 2 other (BIG) */
#define	TT_FILL_3_OTHER  	0xec	/* fill 3 other (BIG) */
#define	TT_FILL_4_OTHER  	0xf0	/* fill 4 other (BIG) */
#define	TT_FILL_5_OTHER  	0xf4	/* fill 5 other (BIG) */
#define	TT_FILL_6_OTHER  	0xf8	/* fill 6 other (BIG) */
#define	TT_FILL_7_OTHER  	0xfc	/* fill 7 other (BIG) */
#define	TT_SWTRAP_BASE		0x100	/* trap instruction */

#ifdef __cplusplus
}
#endif

#endif /* _SUN4V_TRAPS_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: traps.h
	5	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	7	*
	8	* The above named program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public
	10	* License version 2 as published by the Free Software Foundation.
	11	*
	12	* The above named program is distributed in the hope that it will be
	13	* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public
	18	* License along with this work; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*
	21	* ========== Copyright Header End ============================================
	22	*/
	23	/*
	24	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	25	* Use is subject to license terms.
	26	*/
	27
	28	#ifndef _SUN4V_TRAPS_H
	29	#define _SUN4V_TRAPS_H
	30
	31	#pragma ident "@(#)traps.h 1.10 07/05/03 SMI"
	32
	33	#ifdef __cplusplus
	34	extern "C" {
	35	#endif
	36
	37	#define MAXPTL 2 /* Maximum privileged trap level */
	38	#define MAXPGL 2 /* Maximum privileged globals level */
	39	#define TT_OFFSET_SHIFT 5 /* tt to trap table offset shift */
	40	#define TRAPTABLE_ENTRY_SIZE (8 * 4) /* Eight Instructions */
	41	#define REAL_TRAPTABLE_SIZE (8 * TRAPTABLE_ENTRY_SIZE)
	42	#define TRAPTABLE_SIZE (1 << 14)
	43
	44	/*
	45	* sun4v definition of pstate
	46	*/
	47	#define PSTATE_IE 0x00000002 /* interrupt enable */
	48	#define PSTATE_PRIV 0x00000004 /* privilege */
	49	#define PSTATE_AM 0x00000008 /* address mask */
	50	#define PSTATE_PEF 0x00000010 /* fpu enable */
	51	#define PSTATE_MM_MASK 0x000000c0 /* memory model */
	52	#define PSTATE_MM_SHIFT 0x00000006
	53	#define PSTATE_TLE 0x00000100 /* trap little-endian */
	54	#define PSTATE_CLE 0x00000200 /* current little-endian */
	55	#define PSTATE_TCT 0x00001000 /* trap on control transfer */
	56
	57	#define PSTATE_MM_TSO 0x00
	58	#define PSTATE_MM_PSO 0x40
	59	#define PSTATE_MM_RMO 0x80
	60
	61	#define TSTATE_CWP_SHIFT 0
	62	#define TSTATE_CWP_MASK 0x1f
	63	#define TSTATE_PSTATE_SHIFT 8
	64	#define TSTATE_ASI_SHIFT 24
65	#define TSTATE_ASI_MASK 0xff
66	#define TSTATE_CCR_SHIFT 32
67	#define TSTATE_GL_SHIFT 40
68	#define TSTATE_GL_MASK 0x3
69
70	#define TSTATE_PSTATE_PRIV (PSTATE_PRIV << TSTATE_PSTATE_SHIFT)
71
72	#define TT_GUEST_WATCHDOG 0x2 /* guest watchdog */
73	#define TT_IAX 0x8 /* instruction access exception */
74	#define TT_IMMU_MISS 0x9 /* instruction access MMU miss */
75	#define TT_ILLINST 0x10 /* illegal instruction */
76	#define TT_PRIVOP 0x11 /* privileged opcode */
77	#define TT_UNIMP_LDD 0x12 /* unimplemented LDD */
78	#define TT_UNIMP_STD 0x13 /* unimplemented STD */
79	#define TT_FP_DISABLED 0x20 /* fp disabled */
80	#define TT_FP_IEEE754 0x21 /* fp exception IEEE 754 */
81	#define TT_FP_OTHER 0x22 /* fp exception other */
82	#define TT_TAGOVERFLOW 0x23 /* tag overflow */
83	#define TT_CLEANWIN 0x24 /* cleanwin (BIG) */
84	#define TT_DIV0 0x28 /* division by zero */
85	#define TT_DAX 0x30 /* data access exception */
86	#define TT_DMMU_MISS 0x31 /* data access MMU miss */
87	#define TT_DAP 0x33 /* data access protection */
88	#define TT_ALIGN 0x34 /* mem address not aligned */
89	#define TT_LDDF_ALIGN 0x35 /* LDDF mem address not aligned */
90	#define TT_STDF_ALIGN 0x36 /* STDF mem address not aligned */
91	#define TT_PRIVACT 0x37 /* privileged action */
92	#define TT_LDQF_ALIGN 0x38 /* LDQF mem address not aligned */
93	#define TT_STQF_ALIGN 0x39 /* STQF mem address not aligned */
94	#define TT_INTR_LEV1 0x41 /* interrupt level 1 */
95	#define TT_INTR_LEV2 0x42 /* interrupt level 2 */
96	#define TT_INTR_LEV3 0x43 /* interrupt level 3 */
97	#define TT_INTR_LEV4 0x44 /* interrupt level 4 */
98	#define TT_INTR_LEV5 0x45 /* interrupt level 5 */
99	#define TT_INTR_LEV6 0x46 /* interrupt level 6 */
100	#define TT_INTR_LEV7 0x47 /* interrupt level 7 */
101	#define TT_INTR_LEV8 0x48 /* interrupt level 8 */
102	#define TT_INTR_LEV9 0x49 /* interrupt level 9 */
103	#define TT_INTR_LEVa 0x4a /* interrupt level a */
104	#define TT_INTR_LEVb 0x4b /* interrupt level b */
105	#define TT_INTR_LEVc 0x4c /* interrupt level c */
106	#define TT_INTR_LEVd 0x4d /* interrupt level d */
107	#define TT_INTR_LEVe 0x4e /* interrupt level e */
108	#define TT_INTR_LEVf 0x4f /* interrupt level f */
109	#define TT_RA_WATCH 0x61 /* real address watchpoint */
110	#define TT_VA_WATCH 0x62 /* virtual address watchpoint */
111	#define TT_FAST_IMMU_MISS 0x64 /* fast immu miss (BIG) */
112	#define TT_FAST_DMMU_MISS 0x68 /* fast dmmu miss (BIG) */
113	#define TT_FAST_DMMU_PROT 0x6c /* fast dmmu protection (BIG) */
114	#define TT_CTI_TAKEN 0x74 /* control transfer instruction */
115	#define TT_CPU_MONDO 0x7c /* cpu mondo */
116	#define TT_DEV_MONDO 0x7d /* dev mondo */
117	#define TT_RESUMABLE_ERR 0x7e /* resumable error */
118	#define TT_NONRESUMABLE_ERR 0x7f /* non-resumable error */
119	#define TT_SPILL_0_NORMAL 0x80 /* spill 0 normal (BIG) */
120	#define TT_SPILL_1_NORMAL 0x84 /* spill 1 normal (BIG) */
121	#define TT_SPILL_2_NORMAL 0x88 /* spill 2 normal (BIG) */
122	#define TT_SPILL_3_NORMAL 0x8c /* spill 3 normal (BIG) */
123	#define TT_SPILL_4_NORMAL 0x90 /* spill 4 normal (BIG) */
124	#define TT_SPILL_5_NORMAL 0x94 /* spill 5 normal (BIG) */
125	#define TT_SPILL_6_NORMAL 0x98 /* spill 6 normal (BIG) */
126	#define TT_SPILL_7_NORMAL 0x9c /* spill 7 normal (BIG) */
127	#define TT_SPILL_0_OTHER 0xa0 /* spill 0 other (BIG) */
128	#define TT_SPILL_1_OTHER 0xa4 /* spill 1 other (BIG) */
129	#define TT_SPILL_2_OTHER 0xa8 /* spill 2 other (BIG) */
130	#define TT_SPILL_3_OTHER 0xac /* spill 3 other (BIG) */
131	#define TT_SPILL_4_OTHER 0xb0 /* spill 4 other (BIG) */
132	#define TT_SPILL_5_OTHER 0xb4 /* spill 5 other (BIG) */
133	#define TT_SPILL_6_OTHER 0xb8 /* spill 6 other (BIG) */
134	#define TT_SPILL_7_OTHER 0xbc /* spill 7 other (BIG) */
135	#define TT_FILL_0_NORMAL 0xc0 /* fill 0 normal (BIG) */
136	#define TT_FILL_1_NORMAL 0xc4 /* fill 1 normal (BIG) */
137	#define TT_FILL_2_NORMAL 0xc8 /* fill 2 normal (BIG) */
138	#define TT_FILL_3_NORMAL 0xcc /* fill 3 normal (BIG) */
139	#define TT_FILL_4_NORMAL 0xd0 /* fill 4 normal (BIG) */
140	#define TT_FILL_5_NORMAL 0xd4 /* fill 5 normal (BIG) */
141	#define TT_FILL_6_NORMAL 0xd8 /* fill 6 normal (BIG) */
142	#define TT_FILL_7_NORMAL 0xdc /* fill 7 normal (BIG) */
143	#define TT_FILL_0_OTHER 0xe0 /* fill 0 other (BIG) */
144	#define TT_FILL_1_OTHER 0xe4 /* fill 1 other (BIG) */
145	#define TT_FILL_2_OTHER 0xe8 /* fill 2 other (BIG) */
146	#define TT_FILL_3_OTHER 0xec /* fill 3 other (BIG) */
147	#define TT_FILL_4_OTHER 0xf0 /* fill 4 other (BIG) */
148	#define TT_FILL_5_OTHER 0xf4 /* fill 5 other (BIG) */
149	#define TT_FILL_6_OTHER 0xf8 /* fill 6 other (BIG) */
150	#define TT_FILL_7_OTHER 0xfc /* fill 7 other (BIG) */
151	#define TT_SWTRAP_BASE 0x100 /* trap instruction */
152
153	#ifdef __cplusplus
154	}
155	#endif
156
157	#endif /* _SUN4V_TRAPS_H */