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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / t1_fpga / src / xilinx / configs / 2c4t_hv.desc
CommitLineData
920dae64
AT		 1/*
2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
3 * Use is subject to license terms.
4 */
5
6/*
7 * The machine description files are derived from machine description
8 * binaries in OpenSPARC T2 legion simulation directory.
9 */
10
11#include "xilinx_t1_system_config.h"
12
13node root root {
14
15 content-version = 0x100000000;
16 stick-frequency = T1_FPGA_STICK_FREQ;
17 fwd -> platform;
18 fwd -> guests;
19 fwd -> cpus;
20 fwd -> memory;
21 fwd -> maus;
22 fwd -> cwqs;
23 fwd -> devices;
24 fwd -> ldc_endpoints;
25 fwd -> consoles;
26 fwd -> frag_space;
27 hvuart = T1_FPGA_UART_BASE;
28 tod = 0x0;
29}
30
31
32node platform platform {
33
34 back -> root;
35 stick-frequency = T1_FPGA_STICK_FREQ;
36}
37
38
39node guests guests {
40
41 back -> root;
42 fwd -> guest;
43}
44
45
46node cpus cpus {
47
48 back -> root;
49 fwd -> cpu;
50 fwd -> cpu_1;
51 fwd -> cpu_2;
52 fwd -> cpu_3;
53 fwd -> cpu_4;
54 fwd -> cpu_5;
55 fwd -> cpu_6;
56 fwd -> cpu_7;
57}
58
59
60node memory memory {
61
62 back -> root;
63 fwd -> mblock;
64}
65
66
67node maus maus {
68
69 back -> root;
70}
71
72
73node cwqs cwqs {
74
75 back -> root;
76}
77
78
79node devices devices {
80
81 back -> root;
82 fwd -> pcie_bus;
83}
84
85
86node ldc_endpoints ldc_endpoints {
87
88 back -> root;
89 fwd -> ldc_endpoint;
90 fwd -> ldc_endpoint_1;
91 fwd -> ldc_endpoint_2;
92 fwd -> ldc_endpoint_3;
93}
94
95
96node consoles consoles {
97
98 back -> root;
99 fwd -> console;
100}
101
102
103node guest guest {
104
105 back -> guests;
106 name = "domain0";
107 gid = 0x0;
108 resource_id = 0x0;
109 pid = 0x1;
110 tod-offset = 0x0;
111 reset-reason = 0x0;
112 perfctraccess = 0x0;
113 perfctrhtaccess = 0x0;
114 rngctlaccessible = 0x0;
115 diagpriv = 0x0;
116 fwd -> virtual_devices;
117 fwd -> channel_devices;
118 fwd -> pcie_bus;
119 fwd -> cpu;
120 fwd -> cpu_1;
121 fwd -> cpu_2;
122 fwd -> cpu_3;
123 fwd -> cpu_4;
124 fwd -> cpu_5;
125 fwd -> cpu_6;
126 fwd -> cpu_7;
127 fwd -> mblock;
128 mdpa = T1_FPGA_GUEST_MD_ADDR;
129 fwd -> ldc_endpoint;
130 fwd -> ldc_endpoint_1;
131 fwd -> ldc_endpoint_3;
132 rombase = ROMBASE;
133 romsize = ROMSIZE;
134 nvbase = T1_FPGA_NVRAM_ADDR;
135 nvsize = T1_FPGA_NVRAM_SIZE;
136 diskpa = T1_FPGA_RAM_DISK_ADDR;
137 fwd -> console;
138 fwd -> snet;
139}
140
141
142node virtual_devices virtual_devices {
143
144 back -> guest;
145 cfghandle = 0x100;
146}
147
148
149node channel_devices channel_devices {
150
151 back -> guest;
152 cfghandle = 0x200;
153}
154
155
156node pcie_bus pcie_bus {
157
158 back -> guest;
159 back -> devices;
160 resource_id = 0x0;
161 cfghandle = 0x0;
162 gid = 0x0;
163}
164
165
166node cpu cpu {
167
168 back -> cpus;
169 back -> guest;
170 pid = 0x0;
171 vid = 0x0;
172 resource_id = 0x0;
173 gid = 0x0;
174 partid = 0x1;
175}
176
177node cpu cpu_1 {
178
179 back -> cpus;
180 back -> guest;
181 pid = 0x1;
182 vid = 0x1;
183 resource_id = 0x1;
184 gid = 0x0;
185 partid = 0x1;
186}
187
188
189node cpu cpu_2 {
190
191 back -> cpus;
192 back -> guest;
193 pid = 0x2;
194 vid = 0x2;
195 resource_id = 0x2;
196 gid = 0x0;
197 partid = 0x1;
198}
199
200
201node cpu cpu_3 {
202
203 back -> cpus;
204 back -> guest;
205 pid = 0x3;
206 vid = 0x3;
207 resource_id = 0x3;
208 gid = 0x0;
209 partid = 0x1;
210}
211
212node cpu cpu_4 {
213
214 back -> cpus;
215 back -> guest;
216 pid = 0x4;
217 vid = 0x4;
218 resource_id = 0x4;
219 gid = 0x0;
220 partid = 0x1;
221}
222
223node cpu cpu_5 {
224
225 back -> cpus;
226 back -> guest;
227 pid = 0x5;
228 vid = 0x5;
229 resource_id = 0x5;
230 gid = 0x0;
231 partid = 0x1;
232}
233
234node cpu cpu_6 {
235
236 back -> cpus;
237 back -> guest;
238 pid = 0x6;
239 vid = 0x6;
240 resource_id = 0x6;
241 gid = 0x0;
242 partid = 0x1;
243}
244
245node cpu cpu_7 {
246
247 back -> cpus;
248 back -> guest;
249 pid = 0x7;
250 vid = 0x7;
251 resource_id = 0x7;
252 gid = 0x0;
253 partid = 0x1;
254}
255
256node mblock mblock {
257
258 back -> memory;
259 back -> guest;
260 membase = T1_FPGA_GUEST_MEMBASE;
261 memsize = T1_FPGA_GUEST_MEMSIZE;
262 realbase = T1_FPGA_GUEST_REALBASE;
263 resource_id = 0x0;
264}
265
266
267node ldc_endpoint ldc_endpoint {
268
269 back -> ldc_endpoints;
270 back -> guest;
271 target_type = 0x1;
272 channel = 0x0;
273 resource_id = 0x0;
274 tx-ino = 0x0;
275 rx-ino = 0x1;
276 target_channel = 0x0;
277 server_name = "hvctl";
278 server_ldom_name = "domain0";
279 server_instance = 0x0;
280}
281
282
283node ldc_endpoint ldc_endpoint_1 {
284
285 back -> ldc_endpoints;
286 back -> guest;
287 target_type = 0x0;
288 channel = 0x1;
289 resource_id = 0x2;
290 tx-ino = 0x2;
291 rx-ino = 0x3;
292 target_guest = 0x0;
293 target_channel = 0x2;
294 server_name = "vldc";
295 server_ldom_name = "domain0";
296 server_instance = 0x0;
297 client_ldom_name = "domain0";
298}
299
300
301node ldc_endpoint ldc_endpoint_2 {
302
303 back -> ldc_endpoints;
304 target_type = 0x0;
305 channel = 0x0;
306 resource_id = 0x1;
307 target_guest = 0x0;
308 target_channel = 0x0;
309 server_name = "hvctl";
310 server_ldom_name = "domain0";
311 svc_id = 0x1;
312}
313
314
315node ldc_endpoint ldc_endpoint_3 {
316
317 back -> ldc_endpoints;
318 back -> guest;
319 target_type = 0x0;
320 channel = 0x2;
321 resource_id = 0x3;
322 tx-ino = 0x4;
323 rx-ino = 0x5;
324 target_guest = 0x0;
325 target_channel = 0x1;
326 server_name = "vldc";
327 server_ldom_name = "domain0";
328 server_instance = 0x0;
329 client_ldom_name = "domain0";
330}
331
332
333node frag_space frag_space {
334
335 back -> root;
336 fragsize = 0x80000;
337 fwd -> frag_mblock;
338}
339
340
341node frag_mblock frag_mblock {
342
343 back -> frag_space;
344 base = 0x80000;
345 size = 0x180000;
346}
347
348
349node console console {
350
351 back -> consoles;
352 back -> guest;
353 ino = 0x11;
354 resource_id = 0x0;
355 uartbase = T1_FPGA_UART_BASE;
356}
357
358
359node snet snet {
360 back -> guest;
361 snet_ino = T1_FPGA_SNET_INO;
362 resource_id = 0x0;
363 snet_pa = T1_FPGA_SNET_BASE;
364}
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.