[OpenSPARC-T2-SAM] / t1_fpga / src / xilinx / include / xilinx_t1_system_config.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: xilinx_t1_system_config.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _XILINX_T1_SYSTEM_CONFIG_H
#define _XILINX_T1_SYSTEM_CONFIG_H


#define T1_FPGA_PROM_BASE_ADDR            0xfff0000000
#define T1_FPGA_RAM_DISK_ADDR             0xfff1000000

#define T1_FPGA_UART_BASE                 0xfff0c2c000

/* 
 * OpenSPARC T1 frequency as reported to OS. A higher frequency is reported so that one second of time
 * in the FPGA system (running at 50Mhz) is 10 seconds of wall clock time. There are assumptions made in
 * OS (kernel as well as user) that certain activity will be completed in X amount of time. Otherwise
 * OS will timeout and/or panic. Since the FPGA system is slow, the timeout is effectively raised by
 * 10 times to prevent timeouts and/or panics.
 */

#define T1_FPGA_STICK_FREQ                1000000000  /* OpenSPARC T1 frequency as reported to OS */

#define T1_FPGA_SNET_BASE                 0xfff0c2c050
#define T1_FPGA_SNET_INO                  0x3F


#define T1_FPGA_HV_MEMBASE	          0x00000000
#define T1_FPGA_HV_MEMSIZE	          0x01000000

/*
 * Linux needs memory size to be a multiple of 4MB.
 */
#define T1_FPGA_TOTAL_MEMSIZE	          0x0AC00000  /* OpenSPARC T1 DRAM size */


#define T1_FPGA_GUEST_MEMBASE             (T1_FPGA_HV_MEMBASE + T1_FPGA_HV_MEMSIZE)
#define T1_FPGA_GUEST_MEMSIZE             (T1_FPGA_TOTAL_MEMSIZE - T1_FPGA_HV_MEMSIZE)
#define T1_FPGA_GUEST_REALBASE            T1_FPGA_GUEST_MEMBASE


/*
 * Offsets of various binaries stored in PROM. The first three
 * binaries are reset, hypervisor (q) and openboot (OBP) executables.
 * The executables are followed by machine descriptions of guest and
 * hypervisor. The machine description is followed by NVRAM
 */

#define T1_FPGA_PROM_RESET_OFFSET         0x00000
#define T1_FPGA_PROM_MAX_RESET_SIZE       0x20000

#define T1_FPGA_PROM_HV_OFFSET            (T1_FPGA_PROM_RESET_OFFSET + T1_FPGA_PROM_MAX_RESET_SIZE)
#define T1_FPGA_PROM_MAX_HV_SIZE          0x60000

#define T1_FPGA_PROM_OPENBOOT_OFFSET      (T1_FPGA_PROM_HV_OFFSET + T1_FPGA_PROM_MAX_HV_SIZE)
#define T1_FPGA_PROM_MAX_OPENBOOT_SIZE    0x70000

#define T1_FPGA_PROM_GUEST_MD_OFFSET      (T1_FPGA_PROM_OPENBOOT_OFFSET + T1_FPGA_PROM_MAX_OPENBOOT_SIZE)
#define T1_FPGA_PROM_MAX_GUEST_MD_SIZE    0x08000

#define T1_FPGA_PROM_HV_MD_OFFSET         (T1_FPGA_PROM_GUEST_MD_OFFSET + T1_FPGA_PROM_MAX_GUEST_MD_SIZE)
#define T1_FPGA_PROM_MAX_HV_MD_SIZE       0x04000

#define T1_FPGA_PROM_NVRAM_OFFSET         (T1_FPGA_PROM_HV_MD_OFFSET + T1_FPGA_PROM_MAX_HV_MD_SIZE)
#define T1_FPGA_PROM_MAX_NVRAM_SIZE       0x02000
#define T1_FPGA_NVRAM_SIZE                T1_FPGA_PROM_MAX_NVRAM_SIZE

#define T1_FPGA_PROM_BIN_FILE_SIZE        0x100000


#define T1_FPGA_GUEST_MD_ADDR             (T1_FPGA_PROM_BASE_ADDR + T1_FPGA_PROM_GUEST_MD_OFFSET)
#define T1_FPGA_HV_MD_ADDR                (T1_FPGA_PROM_BASE_ADDR + T1_FPGA_PROM_HV_MD_OFFSET)
#define T1_FPGA_NVRAM_ADDR                (T1_FPGA_PROM_BASE_ADDR + T1_FPGA_PROM_NVRAM_OFFSET)


#define T1_FPGA_PROM_HV_START_OFFSET      (T1_FPGA_PROM_HV_OFFSET + 0x20)


#ifdef T1_FPGA_1C4T
#define STRAND_STARTSET   0xf   /* 1c4t configuration */
#elif defined T1_FPGA_2C1T
#define STRAND_STARTSET   0x11   /* 2c1t configuration */
#elif defined T1_FPGA_2C4T
#define STRAND_STARTSET   0xff   /* 2c4t configuration */
#else
#define STRAND_STARTSET   0x1
#endif


/*
 * In Stand-alone mode, the guest executable image is picked up from
 * RAM disk addr. A stand-alone static executable program can be loaded
 * instead of OBP.
 */

#ifdef T1_FPGA_STAND_ALONE

#define ROMBASE        T1_FPGA_RAM_DISK_ADDR
#define ROMSIZE        0x400000

#else /* ifdef T1_FPGA_STAND_ALONE */

#define ROMBASE        (T1_FPGA_PROM_BASE_ADDR + T1_FPGA_PROM_OPENBOOT_OFFSET)
#define ROMSIZE        T1_FPGA_PROM_MAX_OPENBOOT_SIZE

#endif /* ifdef T1_FPGA_STAND_ALONE */


#endif /* ifndef _XILINX_T1_SYSTEM_CONFIG_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: xilinx_t1_system_config.h
	5	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
	7	*
	8	* The above named program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public
	10	* License version 2 as published by the Free Software Foundation.
	11	*
	12	* The above named program is distributed in the hope that it will be
	13	* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public
	18	* License along with this work; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
	20	*
	21	* ========== Copyright Header End ============================================
	22	*/
	23	/*
	24	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	25	* Use is subject to license terms.
	26	*/
	27
	28	#ifndef _XILINX_T1_SYSTEM_CONFIG_H
	29	#define _XILINX_T1_SYSTEM_CONFIG_H
	30
	31
	32
	33	#define T1_FPGA_PROM_BASE_ADDR 0xfff0000000
	34	#define T1_FPGA_RAM_DISK_ADDR 0xfff1000000
	35
	36	#define T1_FPGA_UART_BASE 0xfff0c2c000
	37
	38	/*
	39	* OpenSPARC T1 frequency as reported to OS. A higher frequency is reported so that one second of time
	40	* in the FPGA system (running at 50Mhz) is 10 seconds of wall clock time. There are assumptions made in
	41	* OS (kernel as well as user) that certain activity will be completed in X amount of time. Otherwise
	42	* OS will timeout and/or panic. Since the FPGA system is slow, the timeout is effectively raised by
	43	* 10 times to prevent timeouts and/or panics.
	44	*/
	45
	46	#define T1_FPGA_STICK_FREQ 1000000000 /* OpenSPARC T1 frequency as reported to OS */
	47
	48	#define T1_FPGA_SNET_BASE 0xfff0c2c050
	49	#define T1_FPGA_SNET_INO 0x3F
	50
	51
	52
	53	#define T1_FPGA_HV_MEMBASE 0x00000000
	54	#define T1_FPGA_HV_MEMSIZE 0x01000000
	55
	56	/*
	57	* Linux needs memory size to be a multiple of 4MB.
	58	*/
	59	#define T1_FPGA_TOTAL_MEMSIZE 0x0AC00000 /* OpenSPARC T1 DRAM size */
	60
	61
	62	#define T1_FPGA_GUEST_MEMBASE (T1_FPGA_HV_MEMBASE + T1_FPGA_HV_MEMSIZE)
	63	#define T1_FPGA_GUEST_MEMSIZE (T1_FPGA_TOTAL_MEMSIZE - T1_FPGA_HV_MEMSIZE)
	64	#define T1_FPGA_GUEST_REALBASE T1_FPGA_GUEST_MEMBASE
65
66
67	/*
68	* Offsets of various binaries stored in PROM. The first three
69	* binaries are reset, hypervisor (q) and openboot (OBP) executables.
70	* The executables are followed by machine descriptions of guest and
71	* hypervisor. The machine description is followed by NVRAM
72	*/
73
74	#define T1_FPGA_PROM_RESET_OFFSET 0x00000
75	#define T1_FPGA_PROM_MAX_RESET_SIZE 0x20000
76
77	#define T1_FPGA_PROM_HV_OFFSET (T1_FPGA_PROM_RESET_OFFSET + T1_FPGA_PROM_MAX_RESET_SIZE)
78	#define T1_FPGA_PROM_MAX_HV_SIZE 0x60000
79
80	#define T1_FPGA_PROM_OPENBOOT_OFFSET (T1_FPGA_PROM_HV_OFFSET + T1_FPGA_PROM_MAX_HV_SIZE)
81	#define T1_FPGA_PROM_MAX_OPENBOOT_SIZE 0x70000
82
83	#define T1_FPGA_PROM_GUEST_MD_OFFSET (T1_FPGA_PROM_OPENBOOT_OFFSET + T1_FPGA_PROM_MAX_OPENBOOT_SIZE)
84	#define T1_FPGA_PROM_MAX_GUEST_MD_SIZE 0x08000
85
86	#define T1_FPGA_PROM_HV_MD_OFFSET (T1_FPGA_PROM_GUEST_MD_OFFSET + T1_FPGA_PROM_MAX_GUEST_MD_SIZE)
87	#define T1_FPGA_PROM_MAX_HV_MD_SIZE 0x04000
88
89	#define T1_FPGA_PROM_NVRAM_OFFSET (T1_FPGA_PROM_HV_MD_OFFSET + T1_FPGA_PROM_MAX_HV_MD_SIZE)
90	#define T1_FPGA_PROM_MAX_NVRAM_SIZE 0x02000
91	#define T1_FPGA_NVRAM_SIZE T1_FPGA_PROM_MAX_NVRAM_SIZE
92
93	#define T1_FPGA_PROM_BIN_FILE_SIZE 0x100000
94
95
96	#define T1_FPGA_GUEST_MD_ADDR (T1_FPGA_PROM_BASE_ADDR + T1_FPGA_PROM_GUEST_MD_OFFSET)
97	#define T1_FPGA_HV_MD_ADDR (T1_FPGA_PROM_BASE_ADDR + T1_FPGA_PROM_HV_MD_OFFSET)
98	#define T1_FPGA_NVRAM_ADDR (T1_FPGA_PROM_BASE_ADDR + T1_FPGA_PROM_NVRAM_OFFSET)
99
100
101	#define T1_FPGA_PROM_HV_START_OFFSET (T1_FPGA_PROM_HV_OFFSET + 0x20)
102
103
104
105	#ifdef T1_FPGA_1C4T
106	#define STRAND_STARTSET 0xf /* 1c4t configuration */
107	#elif defined T1_FPGA_2C1T
108	#define STRAND_STARTSET 0x11 /* 2c1t configuration */
109	#elif defined T1_FPGA_2C4T
110	#define STRAND_STARTSET 0xff /* 2c4t configuration */
111	#else
112	#define STRAND_STARTSET 0x1
113	#endif
114
115
116
117	/*
118	* In Stand-alone mode, the guest executable image is picked up from
119	* RAM disk addr. A stand-alone static executable program can be loaded
120	* instead of OBP.
121	*/
122
123	#ifdef T1_FPGA_STAND_ALONE
124
125	#define ROMBASE T1_FPGA_RAM_DISK_ADDR
126	#define ROMSIZE 0x400000
127
128	#else /* ifdef T1_FPGA_STAND_ALONE */
129
130	#define ROMBASE (T1_FPGA_PROM_BASE_ADDR + T1_FPGA_PROM_OPENBOOT_OFFSET)
131	#define ROMSIZE T1_FPGA_PROM_MAX_OPENBOOT_SIZE
132
133	#endif /* ifdef T1_FPGA_STAND_ALONE */
134
135
136
137	#endif /* ifndef _XILINX_T1_SYSTEM_CONFIG_H */