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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: TsoCheckerCmd.h | |
5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
7 | * | |
8 | * The above named program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public | |
10 | * License version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * The above named program is distributed in the hope that it will be | |
13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public | |
18 | * License along with this work; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | * | |
21 | * ========== Copyright Header End ============================================ | |
22 | */ | |
23 | #ifndef _TSOCHECKERCMD_H | |
24 | #define _TSOCHECKERCMD_H | |
25 | /************************************************************************ | |
26 | ** | |
27 | ** Copyright (C) 2002, Sun Microsystems, Inc. | |
28 | ** | |
29 | ** Sun considers its source code as an unpublished, proprietary | |
30 | ** trade secret and it is available only under strict license provisions. | |
31 | ** This copyright notice is placed here only to protect Sun in the event | |
32 | ** the source is deemed a published work. Disassembly, decompilation, | |
33 | ** or other means of reducing the object code to human readable form | |
34 | ** is prohibited by the license agreement under which this code is | |
35 | ** provided to the user or company in possession of this copy." | |
36 | ** | |
37 | *************************************************************************/ | |
38 | #include <iostream> | |
39 | ||
40 | #include "MemorySyncDefs.h" | |
41 | #include "TsoCheckerDefs.h" | |
42 | ||
43 | namespace Tso { | |
44 | ||
45 | ||
46 | class TsoCheckerCmd { | |
47 | ||
48 | public: | |
49 | /** | |
50 | * Default constructor | |
51 | */ | |
52 | TsoCheckerCmd(); | |
53 | ||
54 | /** | |
55 | * Copy constructor | |
56 | * | |
57 | * @param orig The TsoCheckerCmd object to copy. | |
58 | */ | |
59 | TsoCheckerCmd( const TsoCheckerCmd &orig ); | |
60 | ||
61 | /** | |
62 | * Destructor | |
63 | */ | |
64 | virtual ~TsoCheckerCmd(); | |
65 | ||
66 | /** | |
67 | * Equality operator | |
68 | * | |
69 | * @param rhs The right hand side of the equality operator | |
70 | * @return Return true if this objec and rhs are equal, | |
71 | * otherwise return false | |
72 | */ | |
73 | bool operator==( const TsoCheckerCmd &rhs ) const; | |
74 | ||
75 | /** | |
76 | * Assignment operator | |
77 | * | |
78 | * @param rhs The right hand side of the assignment operator. | |
79 | * @return The lvalue of the assignment. | |
80 | */ | |
81 | const TsoCheckerCmd & operator=( const TsoCheckerCmd &rhs ); | |
82 | ||
83 | /** | |
84 | * Return a string representation of this TsoCheckerCmd object. | |
85 | */ | |
86 | std::string toString() const; | |
87 | ||
88 | /** | |
89 | * Check to see if the node coresponds to a store instruction | |
90 | * Note that atomic is also counted as a store instruction. | |
91 | * @return a boolean to relect this check | |
92 | */ | |
93 | isStore() { return (itype_ == ITYPE_STORE || | |
94 | itype_ == ITYPE_BLOCK_STORE || | |
95 | itype_ == ITYPE_STORE_INIT || | |
96 | itype_ == ITYPE_ATOMIC); } | |
97 | ||
98 | /** | |
99 | * Check to see if the node coresponds to a load instruction | |
100 | * Note that atomic is also counted as a load instruction. | |
101 | * @return a boolean to relect this check | |
102 | */ | |
103 | isLoad() { return (itype_ == ITYPE_LOAD || | |
104 | itype_ == ITYPE_BLOCK_LOAD || | |
105 | itype_ == ITYPE_QUAD_LOAD || | |
106 | itype_ == ITYPE_DOUBLE_LOAD || | |
107 | itype_ == ITYPE_ATOMIC); } | |
108 | ||
109 | /** | |
110 | * Check to see if the node coresponds to an atomic instruction | |
111 | * @return a boolean to relect this check | |
112 | */ | |
113 | isAtomic() { return (itype_ == ITYPE_ATOMIC); } | |
114 | ||
115 | /** | |
116 | * Check to see if the node's addres is in I/O range | |
117 | * @return a boolean to relect this check | |
118 | */ | |
119 | isIO() { return ((addr_ & IO_ADDR_BIT_MASK) != 0); } | |
120 | ||
121 | /** | |
122 | * Check to see if the node coresponds to a RMO store instruction | |
123 | * @return a boolean to relect this check | |
124 | */ | |
125 | isRmoStore() { return (itype_ == ITYPE_BLOCK_STORE || itype_ == ITYPE_STORE_INIT); } | |
126 | ||
127 | /** | |
128 | * Check to see if the node coresponds to a RMO instruction | |
129 | * @return a boolean to relect this check | |
130 | */ | |
131 | isRMO() { return (itype_ == ITYPE_BLOCK_STORE || | |
132 | itype_ == ITYPE_STORE_INIT || | |
133 | itype_ == ITYPE_BLOCK_LOAD); } | |
134 | ||
135 | /** | |
136 | * Check to see if the node corresponds to a TSO load instruction | |
137 | * A TSO load is defined as a load whose address is not in I/O space | |
138 | * and is not a RMO load | |
139 | * @return a boolean | |
140 | */ | |
141 | isTsoLoad() { return (isLoad() && !isRMO() && !isIO()); } | |
142 | ||
143 | /** | |
144 | * Check to see if the node corresponds to a TSO store instruction | |
145 | * A TSO store is defined as a store whose address is not in I/O space | |
146 | * and is not a RMO store | |
147 | * @return a boolean | |
148 | */ | |
149 | isTsoStore() { return (isStore() && !isRMO() && !isIO()); } | |
150 | ||
151 | /** | |
152 | * Check to see if the node corresponds to a TSO instruction | |
153 | * A TSO instruciton is defined as an instruction whose address is not | |
154 | * in I/O space and is not a RMO instruction | |
155 | * @return a boolean | |
156 | */ | |
157 | isTSO() { return (isTsoLoad() || isTsoStore()); } | |
158 | ||
159 | /** | |
160 | * Check the if the node is MEM_STORE_COMMIT | |
161 | * @return a bollena | |
162 | */ | |
163 | isStoreCommit() { return (cmd_ == MEM_STORE_COMMIT); } | |
164 | ||
165 | /** | |
166 | * Check the if the node is MEM_LOAD_DATA | |
167 | * @return a bollena | |
168 | */ | |
169 | isLoadData() { return (cmd_ == MEM_LOAD_DATA); } | |
170 | ||
171 | /****************************************************************** | |
172 | * Private variable get/set methods | |
173 | ******************************************************************/ | |
174 | void setTime (uint64_t time) { time_ = time; } | |
175 | void setIseq (uint64_t iseq) { iseq_ = iseq; } | |
176 | void setMacc (uint64_t macc) { macc_ = macc; } | |
177 | void setGobs (uint64_t gobs) { gobs_ = gobs; } | |
178 | void setAddr (uint64_t addr) { addr_ = addr; } | |
179 | void setThrdId (uint32_t tid) { tid_ = tid; } | |
180 | void setItype (enum INSTR_TYPE itype) { itype_ = itype; } | |
181 | void setCmd (enum MEM_CMD cmd) { cmd_ = cmd; } | |
182 | void setDsrc (enum DATA_SRC dsrc) { dsrc_ = dsrc; } | |
183 | void setSizeV (uint8_t sizeV) { sizeV_ = sizeV; } | |
184 | void setData (uint64_t data) { data_ = data; } | |
185 | ||
186 | uint64_t getTime() const { return time_; } | |
187 | uint64_t getIseq() const { return iseq_; } | |
188 | uint64_t getMacc() const { return macc_; } | |
189 | uint64_t getGobs() const { return gobs_; } | |
190 | uint64_t getAddr() const { return addr_; } | |
191 | uint64_t getData() const { return data_; } | |
192 | uint32_t getThrdId() const { return tid_; } | |
193 | enum INSTR_TYPE getItype() const { return itype_; } | |
194 | enum MEM_CMD getCmd() const { return cmd_; } | |
195 | enum DATA_SRC getDsrc() const { return dsrc_; } | |
196 | uint8_t getSizeV() const { return sizeV_; } | |
197 | ||
198 | ||
199 | protected: | |
200 | ||
201 | private: | |
202 | /** | |
203 | * iseq_ is the load/store instruction sequence, must consecutive | |
204 | * but can be out-of-order | |
205 | */ | |
206 | uint64_t iseq_; | |
207 | ||
208 | /** | |
209 | * time_ is when the access happens | |
210 | */ | |
211 | uint64_t time_; | |
212 | ||
213 | /** | |
214 | * macc_ has different definitions for store and load. <br> | |
215 | * <p> | |
216 | * For store it is the time when a store commits (for N2, | |
217 | * it is the time when the data is written into L2 and can be seen | |
218 | * by other L2 access). <br> | |
219 | * <p> | |
220 | * For load, it is any time in the duration when the whole data can | |
221 | * be seen in an L2 access. Note the source of a load may come from | |
222 | * several stores. | |
223 | */ | |
224 | uint64_t macc_; | |
225 | ||
226 | /** | |
227 | * gobs_ is the global observed time of a store. Note that a store | |
228 | * may have stale data in L1 caches of other cores, or caches of | |
229 | * other chips. Before a store data can be globally observed, all | |
230 | * those stale data must be either invalidated or be updated. <br> | |
231 | * <p> | |
232 | * The gobs_ must be no earlier than its L2 commit time, macc_. | |
233 | */ | |
234 | uint64_t gobs_; // global observed time | |
235 | ||
236 | /** | |
237 | * addr_ is the physical address. | |
238 | */ | |
239 | uint64_t addr_; // address | |
240 | ||
241 | /** | |
242 | * data_ is either the load data or store data. | |
243 | */ | |
244 | uint64_t data_; | |
245 | ||
246 | /** | |
247 | * tid_ is a flat thread ID; each thread must have a unique ID. | |
248 | */ | |
249 | uint32_t tid_; // thread ID | |
250 | ||
251 | /** | |
252 | * itype_ is the instruction type, such as load, store, block load/store, | |
253 | * etc, whose definition is in | |
254 | * @see MemorySyncDefs.h | |
255 | */ | |
256 | enum INSTR_TYPE itype_; // instruction type | |
257 | ||
258 | /** | |
259 | * cmd_ is the entry type, such as StoreCommit and LoadData, whose | |
260 | * defintion is in | |
261 | * @see MemorySyncDefs.h | |
262 | */ | |
263 | enum MEM_CMD cmd_; // command | |
264 | ||
265 | /** | |
266 | * dsrc_ is the source of a load data, which could be L1, STB, or | |
267 | * L2/Memory. | |
268 | * @see MemorySyncDefs.h | |
269 | */ | |
270 | enum DATA_SRC dsrc_; // data source | |
271 | ||
272 | /** | |
273 | * The data format is as follows: (Big Edian) | |
274 | * | |
275 | * bit 63 0 | |
276 | * +--------+--------+------------+--------+ <br> | |
277 | * data | byte 0 | byte 1 | --- | byte 7 | <br> | |
278 | * (64 bits) +--------+--------+------------+--------+ <br> | |
279 | * | |
280 | * sizeV_: bit 7 bit 6 bit 0 <br> | |
281 | * (8 bits) <br> | |
282 | * | |
283 | * sizeV_ is to indicates which byte is valid: bit 0 for data_[7:0], | |
284 | * bit 1 for data_[15:8], and so on. | |
285 | */ | |
286 | uint8_t sizeV_; // size vector: 1-> valid byte | |
287 | }; | |
288 | ||
289 | } /* namespace Tso */ | |
290 | ||
291 | #endif /* _TSOCHECKERCMD_H */ |