| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * Hypervisor Software File: mmu.h |
| 5 | * |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 7 | * |
| 8 | * - Do no alter or remove copyright notices |
| 9 | * |
| 10 | * - Redistribution and use of this software in source and binary forms, with |
| 11 | * or without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistribution of source code must retain the above copyright notice, |
| 15 | * this list of conditions and the following disclaimer. |
| 16 | * |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, |
| 18 | * this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors |
| 22 | * may be used to endorse or promote products derived from this software |
| 23 | * without specific prior written permission. |
| 24 | * |
| 25 | * This software is provided "AS IS," without a warranty of any kind. |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| 37 | * |
| 38 | * You acknowledge that this software is not designed, licensed or |
| 39 | * intended for use in the design, construction, operation or maintenance of |
| 40 | * any nuclear facility. |
| 41 | * |
| 42 | * ========== Copyright Header End ============================================ |
| 43 | */ |
| 44 | /* |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 46 | * Use is subject to license terms. |
| 47 | */ |
| 48 | |
| 49 | #ifndef _ONTARIO_MMU_H |
| 50 | #define _ONTARIO_MMU_H |
| 51 | |
| 52 | #pragma ident "@(#)mmu.h 1.22 07/05/03 SMI" |
| 53 | |
| 54 | #ifdef __cplusplus |
| 55 | extern "C" { |
| 56 | #endif |
| 57 | |
| 58 | #include <segments.h> |
| 59 | |
| 60 | /* |
| 61 | * Niagara MMU properties |
| 62 | */ |
| 63 | #define NCTXS 8192 |
| 64 | #define NVABITS 48 |
| 65 | |
| 66 | #define PADDR_IO_BIT 39 |
| 67 | |
| 68 | |
| 69 | /* |
| 70 | * Only support TSBs for the two hardware TSB page size indexes. |
| 71 | */ |
| 72 | #define MAX_NTSB 2 |
| 73 | |
| 74 | /* |
| 75 | * ASI_[DI]MMU registers |
| 76 | */ |
| 77 | #define MMU_SFSR 0x18 |
| 78 | #define MMU_SFAR 0x20 |
| 79 | #define MMU_TAG_ACCESS 0x30 |
| 80 | #define MMU_TAG_TARGET 0x00 |
| 81 | #define TAGACC_CTX_LSHIFT (64-13) |
| 82 | #define TAGTRG_CTX_RSHIFT 48 |
| 83 | #define TAGTRG_VA_LSHIFT 22 |
| 84 | |
| 85 | /* |
| 86 | * ASI_[ID]TSBBASE_CTX* |
| 87 | */ |
| 88 | #define TSB_SZ0_ENTRIES 512 |
| 89 | #define TSB_SZ0_SHIFT 9 /* LOG2(TSB_SZ0_ENTRIES) */ |
| 90 | #define TSB_MAX_SZCODE 15 |
| 91 | |
| 92 | /* |
| 93 | * ASI_[ID]TSB_CONFIG_CTX* |
| 94 | */ |
| 95 | #define ASI_TSB_CONFIG_PS1_SHIFT 8 |
| 96 | |
| 97 | #define ITLB_ENTRIES 64 |
| 98 | #define DTLB_ENTRIES 64 |
| 99 | |
| 100 | /* |
| 101 | * ASI_[DI]MMU_DEMAP |
| 102 | */ |
| 103 | #define DEMAP_ALL 0x2 |
| 104 | |
| 105 | /* |
| 106 | * ASI_TLB_INVALIDATE |
| 107 | */ |
| 108 | #define I_INVALIDATE 0x0 |
| 109 | #define D_INVALIDATE 0x8 |
| 110 | |
| 111 | /* |
| 112 | * Niagara SFSR |
| 113 | */ |
| 114 | #define MMU_SFSR_FV (0x1 << 0) |
| 115 | #define MMU_SFSR_OW (0x1 << 1) |
| 116 | #define MMU_SFSR_W (0x1 << 2) |
| 117 | #define MMU_SFSR_CT (0x3 << 4) |
| 118 | #define MMU_SFSR_E (0x1 << 6) |
| 119 | #define MMU_SFSR_FT_MASK (0x7f) |
| 120 | #define MMU_SFSR_FT_SHIFT (7) |
| 121 | #define MMU_SFSR_FT (MMU_SFSR_FT_MASK << MMU_SFSR_FT_SHIFT) |
| 122 | #define MMU_SFSR_ASI_MASK (0xff) |
| 123 | #define MMU_SFSR_ASI_SHIFT (16) |
| 124 | #define MMU_SFSR_ASI (MMU_SFSR_ASI_MASK << MMU_SFSR_ASI_SHIFT) |
| 125 | |
| 126 | #define MMU_SFSR_FT_PRIV (0x01) /* Privilege violation */ |
| 127 | #define MMU_SFSR_FT_SO (0x02) /* side-effect load from E-page */ |
| 128 | #define MMU_SFSR_FT_ATOMICIO (0x04) /* atomic access to IO address */ |
| 129 | #define MMU_SFSR_FT_ASI (0x08) /* illegal ASI/VA/RW/SZ */ |
| 130 | #define MMU_SFSR_FT_NFO (0x10) /* non-load from NFO page */ |
| 131 | #define MMU_SFSR_FT_VARANGE (0x20) /* d-mmu, i-mmu branch, call, seq */ |
| 132 | #define MMU_SFSR_FT_VARANGE2 (0x40) /* i-mmu jmpl or return */ |
| 133 | |
| 134 | /* |
| 135 | * Native (sun4u) tte format |
| 136 | */ |
| 137 | #define TTE4U_V 0x8000000000000000 |
| 138 | #define TTE4U_SZL 0x6000000000000000 |
| 139 | #define TTE4U_NFO 0x1000000000000000 |
| 140 | #define TTE4U_IE 0x0800000000000000 |
| 141 | #define TTE4U_SZH 0x0001000000000000 |
| 142 | #define TTE4U_DIAG 0x0000ff0000000000 |
| 143 | #define TTE4U_PA_SHIFT 13 |
| 144 | #define TTE4U_L 0x0000000000000040 |
| 145 | #define TTE4U_CP 0x0000000000000020 |
| 146 | #define TTE4U_CV 0x0000000000000010 |
| 147 | #define TTE4U_E 0x0000000000000008 |
| 148 | #define TTE4U_P 0x0000000000000004 |
| 149 | #define TTE4U_W 0x0000000000000002 |
| 150 | |
| 151 | /* |
| 152 | * Niagara's sun4v format - bit 61 is lock, which is a SW bit |
| 153 | * in the sun4v spec and must be cleared on TTEs passed from guest. |
| 154 | */ |
| 155 | #define NI_TTE4V_L_SHIFT 61 |
| 156 | |
| 157 | /* BEGIN CSTYLED */ |
| 158 | #define SET_TTE_LOCK_BIT(reg, scr) \ |
| 159 | mov 1, scr ;\ |
| 160 | sllx scr, NI_TTE4V_L_SHIFT, scr ;\ |
| 161 | or reg, scr, reg |
| 162 | |
| 163 | #define CLEAR_TTE_LOCK_BIT(reg, scr) \ |
| 164 | mov 1, scr ;\ |
| 165 | sllx scr, NI_TTE4V_L_SHIFT, scr ;\ |
| 166 | andn reg, scr, reg |
| 167 | |
| 168 | #define RADDR_IS_IO_XCCNEG(addr, scr1) \ |
| 169 | sllx addr, (63 - PADDR_IO_BIT), scr1 ;\ |
| 170 | tst scr1 |
| 171 | /* END CSTYLED */ |
| 172 | |
| 173 | #define MMU_VALID_FLAGS_MASK (MAP_ITLB | MAP_DTLB) |
| 174 | |
| 175 | /* |
| 176 | * Check that only valid flags bits are set and that at least |
| 177 | * one TLB selector is set. If optional flags are added, |
| 178 | * the simplistic 'brz' will have to be changed. |
| 179 | */ |
| 180 | /* BEGIN CSTYLED */ |
| 181 | #define CHECK_MMU_FLAGS(flags, fail_label) \ |
| 182 | brz,pn flags, fail_label ;\ |
| 183 | andncc flags, MMU_VALID_FLAGS_MASK, %g0 ;\ |
| 184 | bnz,pn %xcc, fail_label ;\ |
| 185 | nop |
| 186 | |
| 187 | /* |
| 188 | * Check the virtual address and context for validity |
| 189 | * on Niagara |
| 190 | */ |
| 191 | #define CHECK_CTX(ctx, fail_label, scr) \ |
| 192 | set NCTXS, scr ;\ |
| 193 | cmp ctx, scr ;\ |
| 194 | bgeu,pn %xcc, fail_label ;\ |
| 195 | nop |
| 196 | #define CHECK_VA_CTX(va, ctx, fail_label, scr) \ |
| 197 | sllx va, (64 - NVABITS), scr ;\ |
| 198 | srax scr, (64 - NVABITS), scr ;\ |
| 199 | cmp va, scr ;\ |
| 200 | bne,pn %xcc, fail_label ;\ |
| 201 | CHECK_CTX(ctx, fail_label, scr) |
| 202 | /* END CSTYLED */ |
| 203 | |
| 204 | /* |
| 205 | * Supported page size encodings for Niagara |
| 206 | */ |
| 207 | #define TTE_VALIDSIZEARRAY \ |
| 208 | ((1 << 0) | /* 8K */ \ |
| 209 | (1 << 1) | /* 64k */ \ |
| 210 | (1 << 3) | /* 4M */ \ |
| 211 | (1 << 5)) /* 256M */ |
| 212 | |
| 213 | /* Largest page size is 28bits */ |
| 214 | #define LARGEST_PG_SIZE_BITS 28 |
| 215 | |
| 216 | #ifdef __cplusplus |
| 217 | } |
| 218 | #endif |
| 219 | |
| 220 | #endif /* _ONTARIO_MMU_H */ |