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* Hypervisor Software File: mmu.h
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* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
#pragma ident "@(#)mmu.h 1.22 07/05/03 SMI"
* Only support TSBs for the two hardware TSB page size indexes.
#define MMU_TAG_ACCESS 0x30
#define MMU_TAG_TARGET 0x00
#define TAGACC_CTX_LSHIFT (64-13)
#define TAGTRG_CTX_RSHIFT 48
#define TAGTRG_VA_LSHIFT 22
#define TSB_SZ0_ENTRIES 512
#define TSB_SZ0_SHIFT 9 /* LOG2(TSB_SZ0_ENTRIES) */
#define TSB_MAX_SZCODE 15
* ASI_[ID]TSB_CONFIG_CTX*
#define ASI_TSB_CONFIG_PS1_SHIFT 8
#define MMU_SFSR_FV (0x1 << 0)
#define MMU_SFSR_OW (0x1 << 1)
#define MMU_SFSR_W (0x1 << 2)
#define MMU_SFSR_CT (0x3 << 4)
#define MMU_SFSR_E (0x1 << 6)
#define MMU_SFSR_FT_MASK (0x7f)
#define MMU_SFSR_FT_SHIFT (7)
#define MMU_SFSR_FT (MMU_SFSR_FT_MASK << MMU_SFSR_FT_SHIFT)
#define MMU_SFSR_ASI_MASK (0xff)
#define MMU_SFSR_ASI_SHIFT (16)
#define MMU_SFSR_ASI (MMU_SFSR_ASI_MASK << MMU_SFSR_ASI_SHIFT)
#define MMU_SFSR_FT_PRIV (0x01) /* Privilege violation */
#define MMU_SFSR_FT_SO (0x02) /* side-effect load from E-page */
#define MMU_SFSR_FT_ATOMICIO (0x04) /* atomic access to IO address */
#define MMU_SFSR_FT_ASI (0x08) /* illegal ASI/VA/RW/SZ */
#define MMU_SFSR_FT_NFO (0x10) /* non-load from NFO page */
#define MMU_SFSR_FT_VARANGE (0x20) /* d-mmu, i-mmu branch, call, seq */
#define MMU_SFSR_FT_VARANGE2 (0x40) /* i-mmu jmpl or return */
* Native (sun4u) tte format
#define TTE4U_V 0x8000000000000000
#define TTE4U_SZL 0x6000000000000000
#define TTE4U_NFO 0x1000000000000000
#define TTE4U_IE 0x0800000000000000
#define TTE4U_SZH 0x0001000000000000
#define TTE4U_DIAG 0x0000ff0000000000
#define TTE4U_PA_SHIFT 13
#define TTE4U_L 0x0000000000000040
#define TTE4U_CP 0x0000000000000020
#define TTE4U_CV 0x0000000000000010
#define TTE4U_E 0x0000000000000008
#define TTE4U_P 0x0000000000000004
#define TTE4U_W 0x0000000000000002
* Niagara's sun4v format - bit 61 is lock, which is a SW bit
* in the sun4v spec and must be cleared on TTEs passed from guest.
#define NI_TTE4V_L_SHIFT 61
#define SET_TTE_LOCK_BIT(reg, scr) \
sllx scr, NI_TTE4V_L_SHIFT, scr ;\
#define CLEAR_TTE_LOCK_BIT(reg, scr) \
sllx scr, NI_TTE4V_L_SHIFT, scr ;\
#define RADDR_IS_IO_XCCNEG(addr, scr1) \
sllx addr, (63 - PADDR_IO_BIT), scr1 ;\
#define MMU_VALID_FLAGS_MASK (MAP_ITLB | MAP_DTLB)
* Check that only valid flags bits are set and that at least
* one TLB selector is set. If optional flags are added,
* the simplistic 'brz' will have to be changed.
#define CHECK_MMU_FLAGS(flags, fail_label) \
brz,pn flags, fail_label ;\
andncc flags, MMU_VALID_FLAGS_MASK, %g0 ;\
bnz,pn %xcc, fail_label ;\
* Check the virtual address and context for validity
#define CHECK_CTX(ctx, fail_label, scr) \
bgeu,pn %xcc, fail_label ;\
#define CHECK_VA_CTX(va, ctx, fail_label, scr) \
sllx va, (64 - NVABITS), scr ;\
srax scr, (64 - NVABITS), scr ;\
bne,pn %xcc, fail_label ;\
CHECK_CTX(ctx, fail_label, scr)
* Supported page size encodings for Niagara
#define TTE_VALIDSIZEARRAY \
/* Largest page size is 28bits */
#define LARGEST_PG_SIZE_BITS 28
#endif /* _ONTARIO_MMU_H */