| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: LoadStoreCmd.h |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 7 | * |
| 8 | * The above named program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public |
| 10 | * License version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * The above named program is distributed in the hope that it will be |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public |
| 18 | * License along with this work; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 20 | * |
| 21 | * ========== Copyright Header End ============================================ |
| 22 | */ |
| 23 | #ifndef _LOADSTORECMD_H |
| 24 | #define _LOADSTORECMD_H |
| 25 | /************************************************************************ |
| 26 | ** |
| 27 | ** Copyright (C) 2002, Sun Microsystems, Inc. |
| 28 | ** |
| 29 | ** Sun considers its source code as an unpublished, proprietary |
| 30 | ** trade secret and it is available only under strict license provisions. |
| 31 | ** This copyright notice is placed here only to protect Sun in the event |
| 32 | ** the source is deemed a published work. Disassembly, decompilation, |
| 33 | ** or other means of reducing the object code to human readable form |
| 34 | ** is prohibited by the license agreement under which this code is |
| 35 | ** provided to the user or company in possession of this copy." |
| 36 | ** |
| 37 | *************************************************************************/ |
| 38 | #include <iostream> |
| 39 | |
| 40 | #include "MemorySyncDefs.h" |
| 41 | #include "MemorySyncMessage.h" |
| 42 | #include "RieslingInterface.h" |
| 43 | |
| 44 | |
| 45 | class LoadStoreCmd { |
| 46 | |
| 47 | public: |
| 48 | /** |
| 49 | * Default constructor |
| 50 | */ |
| 51 | LoadStoreCmd(); |
| 52 | |
| 53 | /** |
| 54 | * Set all variables |
| 55 | */ |
| 56 | LoadStoreCmd(enum MEM_CMD cmd, enum INSTR_TYPE itype, uint32_t cid, uint32_t tid, |
| 57 | uint32_t srcTid, uint32_t srcBank, uint32_t inv, uint32_t set, |
| 58 | uint32_t way, uint64_t id, uint64_t addr, uint64_t data, uint8_t size_vector, |
| 59 | uint8_t size, enum DATA_SRC dsrc, bool cacheL1, bool rmo, bool l2hit, |
| 60 | bool switchData, bool ioaddr, uint64_t cycle); |
| 61 | |
| 62 | |
| 63 | /** |
| 64 | * Copy constructor |
| 65 | * |
| 66 | * @param orig The LoadStoreCmd object to copy. |
| 67 | */ |
| 68 | LoadStoreCmd( const LoadStoreCmd &orig ); |
| 69 | |
| 70 | /** |
| 71 | * Destructor |
| 72 | */ |
| 73 | virtual ~LoadStoreCmd(); |
| 74 | |
| 75 | /** |
| 76 | * Equality operator |
| 77 | * |
| 78 | * @param rhs The right hand side of the equality operator |
| 79 | * @return Return true if this objec and rhs are equal, |
| 80 | * otherwise return false |
| 81 | */ |
| 82 | /* bool operator==( const LoadStoreCmd &rhs ) const; */ |
| 83 | |
| 84 | /** |
| 85 | * Assignment operator |
| 86 | * |
| 87 | * @param rhs The right hand side of the assignment operator. |
| 88 | * @return The lvalue of the assignment. |
| 89 | */ |
| 90 | /* const LoadStoreCmd & operator=( const LoadStoreCmd &rhs ); */ |
| 91 | |
| 92 | /** |
| 93 | * Return a string representation of this LoadStoreCmd object. |
| 94 | */ |
| 95 | std::string toString() const; |
| 96 | |
| 97 | /** |
| 98 | * This method initialize ioaddr_, rmoStore_, and rtlCycle variables |
| 99 | */ |
| 100 | void auxInit (); |
| 101 | |
| 102 | /** |
| 103 | * Convert size to byte mask, maximum data is assumed 8 bytes |
| 104 | * <p> |
| 105 | * @param size data size in the unit of byte |
| 106 | * @param aoffset 3 bits address offset |
| 107 | * @return 8 bit size mask in which bit0->byte0, bit1->byte1, etc <br> |
| 108 | * and a bit = 1 => the corresponding byte is valid |
| 109 | */ |
| 110 | uint8_t sz2szv (uint8_t size, uint32_t aoffset); |
| 111 | |
| 112 | /** |
| 113 | * Convert 8 bits byte mask to size |
| 114 | * <p> |
| 115 | * @param szv byte mask with bit0->byte0, bit1->byte1, etc, and <br> |
| 116 | * a bit = 1 => the corresponding byte is valid |
| 117 | * @return data size in the unit of byte, if a non-consecutive pattern of 1s <br> |
| 118 | * is in the szv, then always return 8 |
| 119 | */ |
| 120 | uint8_t szv2sz (uint8_t szv); |
| 121 | |
| 122 | /** |
| 123 | * Convert the size to log2 notation |
| 124 | * @param size data size in the unit of byte |
| 125 | * @return the equivalent log2 representation |
| 126 | */ |
| 127 | uint8_t sz2szlog (uint8_t size); |
| 128 | |
| 129 | /****************************************************************************** |
| 130 | * General variables access methods |
| 131 | ******************************************************************************/ |
| 132 | enum MEM_CMD getCmd() const { return cmd_;} |
| 133 | enum INSTR_TYPE getItype() const { return itype_; } |
| 134 | enum DATA_SRC getDsrc() const { return dsrc_; } |
| 135 | bool isCacheL1() const { return cacheL1_; } |
| 136 | bool isIO() const { return ioaddr_; } |
| 137 | bool isRMOstore() const { return rmoStore_; } |
| 138 | bool isL2hit() const { return l2hit_; } |
| 139 | bool isSwitchData() const { return switchData_; } |
| 140 | uint32_t getCoreId() const { return cid_; } |
| 141 | uint32_t getThrdId() const { return tid_; } |
| 142 | uint32_t getSrcTid() const { return srcTid_; } |
| 143 | uint32_t getSrcBank() const { return srcBank_; } |
| 144 | uint32_t getInv() const { return inv_; } |
| 145 | uint32_t getSet() const { return set_; } |
| 146 | uint32_t getWay() const { return way_; } |
| 147 | uint64_t getCycle() const { return cycle_; } |
| 148 | uint64_t getAddr() const { return addr_; } |
| 149 | uint64_t getId() const { return id_; } |
| 150 | uint64_t getData() const { return data_; } |
| 151 | uint8_t getVbyte() const { return vbyte_; } |
| 152 | uint8_t getSizeV() const { return vbyte_; } |
| 153 | uint8_t getSize() const { return size_; } |
| 154 | int getTsize() { return tsize; } |
| 155 | |
| 156 | void setCmd (enum MEM_CMD cmd) { cmd_ = cmd; } |
| 157 | void setItype (enum INSTR_TYPE itype) { itype_ = itype; } |
| 158 | void setDsrc (enum DATA_SRC dsrc) { dsrc_ = dsrc; } |
| 159 | void setCacheL1 (bool cacheL1) { cacheL1_ = cacheL1; } |
| 160 | void setIOaddr (bool ioaddr) { ioaddr_ = ioaddr; } |
| 161 | void setL2hit (bool l2hit) { l2hit_ = l2hit; } |
| 162 | void setRMOStore (bool rmoStore) { rmoStore_ = rmoStore; } |
| 163 | void setSwitchData (bool switchData) { switchData_ = switchData; } |
| 164 | void setCoreId (uint32_t cid) { cid_ = cid; } |
| 165 | void setThrdId (uint32_t tid) { tid_ = tid; } |
| 166 | void setSrcTid (uint32_t srcTid) { srcTid_ = srcTid; } |
| 167 | void setSrcBank (uint32_t srcBank) { srcBank_ = srcBank; } |
| 168 | void setInv (uint32_t inv) { inv_ = inv; } |
| 169 | void setSet (uint32_t set) { set_ = set; } |
| 170 | void setWay (uint32_t way) { way_ = way; } |
| 171 | void setCycle (uint64_t cycle) { cycle_ = cycle; } |
| 172 | void setAddr (uint64_t addr) { addr_ = addr; } |
| 173 | void setId (uint64_t id) { id_ = id; } |
| 174 | void setData (uint64_t data) { data_ = data; } |
| 175 | void setVbyte (uint8_t vbyte) { vbyte_ = vbyte; } |
| 176 | void setSizeV (uint8_t sizeV) { vbyte_ = sizeV; } |
| 177 | void setSize (uint8_t size) { size_ = size; } |
| 178 | void setTsize(int _tsize) { tsize = _tsize; } |
| 179 | |
| 180 | protected: |
| 181 | /** |
| 182 | * See MemorySyncDefs.h for enum types of MEM_CMD, INSTR_TYPE, and DATA_SRC. |
| 183 | */ |
| 184 | /** |
| 185 | * cmd_ is the command type associated with the MemorySync APIs |
| 186 | * @see MemorySyncDefs.h |
| 187 | */ |
| 188 | enum MEM_CMD cmd_; // memory operation command |
| 189 | |
| 190 | /** |
| 191 | * itype_ is the instruction type |
| 192 | * @see MemorySyncDefs.h |
| 193 | */ |
| 194 | enum INSTR_TYPE itype_; // instruction type |
| 195 | |
| 196 | /** |
| 197 | * dsrc_ is the data source |
| 198 | * @see MemorySyncDefs.h |
| 199 | */ |
| 200 | enum DATA_SRC dsrc_; // data source |
| 201 | |
| 202 | /** |
| 203 | * cacheL1_ indicates if the data needs to be cached in L1 |
| 204 | */ |
| 205 | bool cacheL1_; // true: data to be cached in L1; false: otherwise |
| 206 | |
| 207 | /** |
| 208 | * ioaddr_ indicates if the access is to I/O address space |
| 209 | */ |
| 210 | bool ioaddr_; // true: I/O address range; false: otherwise |
| 211 | |
| 212 | /** |
| 213 | * rmoStore_ is to indicates if a store is a RMO store. |
| 214 | * <p> |
| 215 | * The term RMO store is borrowed from Niagara. It means a store that does not |
| 216 | * perform dependence check and follows RMO memory consistency model. This type |
| 217 | * of stores includes Block Store and BLK_INIT store. |
| 218 | * |
| 219 | * In N2, a RMO store is removed from the store buffer when it is issued from |
| 220 | * the store buffer. Other types of stores will remain in the store buffer after |
| 221 | * its data is committed to the memory hierarchy (this is a simple approach to |
| 222 | * comply with TSO). Hence, the StoreAck of a RMO store is issued before its |
| 223 | * Storecommit; while the StoreAck of other type of store is issued after its |
| 224 | * Storecommit. In addition, although StoreAcks of a sequence of RMO stores |
| 225 | * remain in order, a non-RMO following an RMO could get out of order. |
| 226 | */ |
| 227 | bool rmoStore_; // true: the store is a RMO store; false: otherwise |
| 228 | |
| 229 | /** |
| 230 | * l2hit_ indicates a reference hits L2 or not. |
| 231 | * <p> |
| 232 | * In general, the Memory Sync model does not care whether an access is L2 hit |
| 233 | * or not. The l2hit_ boolean defined here is for special cases. |
| 234 | * |
| 235 | * One example is the BLK_INIT store defined in Niagara 1 and 2. The behavior |
| 236 | * of this type of store also depends on whether it hits L2 or not. Normally, |
| 237 | * this is just another RMO store. However, if the following 3 conditions are |
| 238 | * satisfied, then the addressed 64-byte chunk becomes 0 before the store data |
| 239 | * is written: |
| 240 | * - the 6 least significant bits of the address are 0, |
| 241 | * - the address is not within I/O address space, and |
| 242 | * - the acecss is not L2 hit |
| 243 | */ |
| 244 | bool l2hit_; // true: the access hits L2; false: otherwise |
| 245 | |
| 246 | |
| 247 | /** |
| 248 | * switchData_ indicates if the memory data will be changed for an atomic instruction. |
| 249 | * <p> |
| 250 | * Atomic instruction consists of two parts: load and store. However, for CAS |
| 251 | * instruction, if the comparison is a false, then the value of the addressed |
| 252 | * memory is not changed. In this case, Riesling won't send a store transaction |
| 253 | * to the memory, thus no store side callback. The switchData_ is false only if |
| 254 | * the atomic instruction is a CAS and its comparsion results in a false. |
| 255 | */ |
| 256 | bool switchData_; |
| 257 | |
| 258 | /****************************************************************************** |
| 259 | * In Memory Sync Model notation, a core is an entity that contains L1 cache. |
| 260 | * Threads that share the same L1 cache belong to the same core. |
| 261 | ******************************************************************************/ |
| 262 | |
| 263 | /** |
| 264 | * cid_ is the core id |
| 265 | */ |
| 266 | uint32_t cid_; // core id |
| 267 | |
| 268 | /** |
| 269 | * tid_ is the flat thread id. <br> |
| 270 | * If a core has n threads, then the tid_ of core 0 will be in [0, n-1], |
| 271 | * the tid_ of core 1 will be in [n, 2n-1], and so on |
| 272 | */ |
| 273 | uint32_t tid_; // (global) thread id |
| 274 | |
| 275 | /** |
| 276 | * srcTid_ indicates the source thread that initiates an event, e.g., StoreInv |
| 277 | */ |
| 278 | uint32_t srcTid_; // source thread id that trigger this event, used in STORE_INV |
| 279 | /** |
| 280 | * srcBank_ is the bank that initiates an event, e.g., EVICT |
| 281 | */ |
| 282 | uint32_t srcBank_; // source bank id where the event occurs, used in EVICT |
| 283 | |
| 284 | /** |
| 285 | * inv_ is L1 cache invalidation vector that reflects the directory info of |
| 286 | * a L2 cache line. Each bit corresponds a core: bit 0 -> core 0, bit 1 -> |
| 287 | * core 1, and so on. That a bit is 1 indicates the cache line exists in the |
| 288 | * corresponding core. The least significant bits of inv_ are used for D$; |
| 289 | * and the most significant bits are used for I$. |
| 290 | */ |
| 291 | uint32_t inv_; // L1 cache invalidation vector, bit0 -> core0, bit1 -> core1, etc. |
| 292 | |
| 293 | /** |
| 294 | * set_ is the cache set |
| 295 | */ |
| 296 | uint32_t set_; // set of a cache |
| 297 | |
| 298 | /** |
| 299 | * way_ is the way info of a cache |
| 300 | */ |
| 301 | uint32_t way_; // way of a cache |
| 302 | |
| 303 | /** |
| 304 | * addr_ is the physical address |
| 305 | */ |
| 306 | uint64_t addr_; // address |
| 307 | |
| 308 | /** |
| 309 | * id_ is a unique number |
| 310 | * <p> |
| 311 | * The id_ field is to be used in out-of-order environment so that commands can |
| 312 | * be mapped with LoadIssue/StoreIssue. In the in-order environment, where load |
| 313 | * and store mostly follow some in-order rules, this field is not used. |
| 314 | * Niagara 1 and Niagara 2 do not use this field. |
| 315 | */ |
| 316 | uint64_t id_; // unique number for matching other mem_cmd for the same instr. |
| 317 | |
| 318 | /** |
| 319 | * cycle_ is the RTL cycle when the command happens. |
| 320 | */ |
| 321 | uint64_t cycle_; // the RTL cycle when the command happens |
| 322 | |
| 323 | /** |
| 324 | * data_ is the data for the memory operation |
| 325 | * <p> |
| 326 | * The data format MemorySync model expects on STOREs is as follows: (Big Edian) |
| 327 | * |
| 328 | * bit 63 0<br> |
| 329 | * +--------+--------+------------+--------+<br> |
| 330 | * data | byte 0 | byte 1 | --- | byte 7 |<br> |
| 331 | * (64 bits) +--------+--------+------------+--------+<br> |
| 332 | * |
| 333 | * size_vector: bit 7 bit 6 bit 0<br> |
| 334 | * (8 bits)<br> |
| 335 | */ |
| 336 | uint64_t data_; // data |
| 337 | |
| 338 | /** |
| 339 | * vbyte_ is the byte mask as shown in the description of data_ |
| 340 | */ |
| 341 | uint8_t vbyte_; // valid byte mask bit0 -> byte0, bit1 -> byte1, and so on |
| 342 | |
| 343 | /** |
| 344 | * size_ is the data size |
| 345 | */ |
| 346 | uint8_t size_; // size of data |
| 347 | |
| 348 | /** |
| 349 | * used in DMA_STORE, a DMA_STORE operation can be 8 bytes or 64 bytes, |
| 350 | * testbench will break it into 8 byte per DMA_STORE command, we use the |
| 351 | * totla_size to calculate how many DMA_STORE commands are to be expected, |
| 352 | * the information is also used to handle related EVICT and EVICT_INV, as |
| 353 | * there will be only one EVICT for each DMA_STORE operation (meaning even |
| 354 | * if it is a 64-byte store, we will only see one EVICT). |
| 355 | */ |
| 356 | int tsize; |
| 357 | }; |
| 358 | |
| 359 | |
| 360 | class StoreIssueCmd : public LoadStoreCmd { |
| 361 | public: |
| 362 | /** |
| 363 | * A StoreIssueCmd is issued when a store is inserted into the store buffer |
| 364 | * after address translation |
| 365 | * <P> |
| 366 | * @param itype instruction type associated with this command |
| 367 | * @param tid thread ID for the thread that issues this command |
| 368 | * @param id unique ID to identify this issue |
| 369 | * @param addr the address where the data is written |
| 370 | * @param data the data to be written |
| 371 | * @param size_vector valid byte mask of the data |
| 372 | * @param cycle issued time |
| 373 | */ |
| 374 | StoreIssueCmd(enum INSTR_TYPE itype, |
| 375 | uint32_t tid, |
| 376 | uint64_t id, |
| 377 | uint64_t addr, |
| 378 | uint64_t data, |
| 379 | uint8_t size_vector, |
| 380 | uint64_t cycle); |
| 381 | }; |
| 382 | |
| 383 | class StoreCommitCmd : public LoadStoreCmd { |
| 384 | public: |
| 385 | /** |
| 386 | * A StorecommitCmd is issued when a store whose data is observed in L2 |
| 387 | * (L2 is shared and is writeback in this model) by other thread/cpu |
| 388 | * <p> |
| 389 | * @param tid thread ID for the thread that issues this command |
| 390 | * @param inv L1 cache invalidation vector |
| 391 | * @param id unique ID to identify the StoreIssue corresponding to this StoreCommit |
| 392 | * @param addr the address where the data is written |
| 393 | * @param size_vector this field can be valid byte mask of the data or comparison |
| 394 | * result of a CAS instruction where 0 means false comparison |
| 395 | * @param l2hit the store hit L2$ that is only used to handle BLK_INIT store |
| 396 | * @param cycle issued time |
| 397 | */ |
| 398 | StoreCommitCmd(uint32_t tid, |
| 399 | uint32_t inv, |
| 400 | uint64_t id, |
| 401 | uint64_t addr, |
| 402 | uint8_t size_vector, |
| 403 | bool l2hit, |
| 404 | bool switchData, |
| 405 | uint64_t cycle); |
| 406 | }; |
| 407 | |
| 408 | class StoreInvCmd : public LoadStoreCmd { |
| 409 | public: |
| 410 | /** |
| 411 | * A StoreInv is issued when an invalidation is performed on its L1 cache |
| 412 | * <p> |
| 413 | * @param cid core ID that sees this invalidation |
| 414 | * @param srcTid thread ID that triggers this invalidation |
| 415 | * @param addr the address where the data is written |
| 416 | * @param cycle issued time |
| 417 | */ |
| 418 | StoreInvCmd(uint32_t cid, |
| 419 | uint32_t srcTid, |
| 420 | uint64_t addr, |
| 421 | uint64_t cycle); |
| 422 | }; |
| 423 | |
| 424 | class StoreUpdateCmd : public LoadStoreCmd { |
| 425 | public: |
| 426 | /** |
| 427 | * A StoreUpdate is issued when a update is performed on its L1 cache |
| 428 | * <p> |
| 429 | * @param tid Thrd ID whose store results in this store update |
| 430 | * @param addr the address where the data is written |
| 431 | * @param cycle issued time |
| 432 | */ |
| 433 | StoreUpdateCmd(uint32_t tid, |
| 434 | uint64_t addr, |
| 435 | uint64_t cycle); |
| 436 | }; |
| 437 | |
| 438 | class StoreAckCmd : public LoadStoreCmd { |
| 439 | public: |
| 440 | /** |
| 441 | * A StoreAck is issued when a store is removed from the store buffer |
| 442 | * <p> |
| 443 | * Stores will be checked to see if they are Acked in order. Non-RMO |
| 444 | * stores and RMO stores are checked separately since although they |
| 445 | * should be Acked in order in each group, they can be out-of-order |
| 446 | * between groups. |
| 447 | * <p> |
| 448 | * @param tid Thrd ID which sees the store ack |
| 449 | * @param addr the address where the data is written, always 0 in N2 |
| 450 | * @param rmoStore indicates if the store is a RMO store |
| 451 | * @param cycle issued time |
| 452 | */ |
| 453 | StoreAckCmd(uint32_t tid, |
| 454 | uint64_t addr, |
| 455 | bool rmoStore, |
| 456 | uint64_t cycle); |
| 457 | }; |
| 458 | |
| 459 | class LoadIssueCmd : public LoadStoreCmd { |
| 460 | public: |
| 461 | /** |
| 462 | * A LoadIssue is issued when in RTL a load is issued from an in-order domain to |
| 463 | * an out-of-order domain |
| 464 | * <p> |
| 465 | * @param itype instruction type associated with this command |
| 466 | * @param tid thread ID for the thread that issues this command |
| 467 | * @param id unique ID to identify this issue |
| 468 | * @param addr the address of the data to be loaded |
| 469 | * @param size size of to be loaded data |
| 470 | * @param cacheL1 boolean to determine if the load access should be place in L1$ |
| 471 | * @param cycle issued time |
| 472 | */ |
| 473 | LoadIssueCmd(enum INSTR_TYPE itype, |
| 474 | uint32_t tid, |
| 475 | uint64_t id, |
| 476 | uint64_t addr, |
| 477 | uint8_t size, |
| 478 | bool cacheL1, |
| 479 | uint64_t cycle); |
| 480 | }; |
| 481 | |
| 482 | class LoadDataCmd : public LoadStoreCmd { |
| 483 | public: |
| 484 | /** |
| 485 | * A LoadData is issued when a load gets its data |
| 486 | * <p> |
| 487 | * @param tid thread ID for the thread that issues this command |
| 488 | * @param id unique ID to identify the LoadIssue corresponding to this LoadData |
| 489 | * @param addr the address where the data is loaded |
| 490 | * @param size size of to be loaded data |
| 491 | * @param dsrc data source, either from L1, STB, or L2/Memory |
| 492 | * @param cacheL1 boolean to determine if the load access should be place in L1$ |
| 493 | * @param cycle issued time |
| 494 | */ |
| 495 | LoadDataCmd(uint32_t tid, |
| 496 | uint64_t id, |
| 497 | uint64_t addr, |
| 498 | uint8_t size, |
| 499 | enum DATA_SRC dsrc, |
| 500 | bool cacheL1, |
| 501 | uint64_t cycle); |
| 502 | }; |
| 503 | |
| 504 | class LoadFillCmd : public LoadStoreCmd { |
| 505 | public: |
| 506 | /** |
| 507 | * A LoadFill is issued when a line is filled into L1 and the new data can be |
| 508 | * seen by next access from the same core |
| 509 | * <p> |
| 510 | * @param tid thread ID for the thread whose load results in this line fill |
| 511 | * @param id unique ID to identify the load resulting in this line fill |
| 512 | * @param addr the address where the data is written |
| 513 | * @param cycle issued time |
| 514 | */ |
| 515 | LoadFillCmd(uint32_t tid, |
| 516 | uint64_t id, |
| 517 | uint64_t addr, |
| 518 | uint64_t cycle); |
| 519 | }; |
| 520 | |
| 521 | class EvictCmd : public LoadStoreCmd { |
| 522 | public: |
| 523 | /** |
| 524 | * An Evict is issued When a line is evicted from L2 which will in turn |
| 525 | * invalid line in L1. A L2 line eviction may cause invalidation of |
| 526 | * multiple L1 lines. The MemorySync expects one Evict packet for each |
| 527 | * L1 cache line since each cache line may have different invalidation |
| 528 | * vector. |
| 529 | * <p> |
| 530 | * @param inv L1 cache invalidation vector |
| 531 | * @param set L1 cache set of the evicted line |
| 532 | * @param way L1 cache way of the evicted line |
| 533 | * @param addr the address of the evict line |
| 534 | * @param cycle issued time |
| 535 | */ |
| 536 | EvictCmd(uint32_t inv, |
| 537 | uint32_t set, |
| 538 | uint32_t way, |
| 539 | uint64_t addr, |
| 540 | uint64_t cycle); |
| 541 | }; |
| 542 | |
| 543 | class EvictInvCmd : public LoadStoreCmd { |
| 544 | public: |
| 545 | /** |
| 546 | * A EvictInv is issued when an invalidation is performed on its L1 cache |
| 547 | * <p> |
| 548 | * @param cid core ID that sees this invalidation |
| 549 | * @param srcBank bank ID that triggers this invalidation |
| 550 | * @param set L1 cache set of the invalidated line affected by the eviction |
| 551 | * @param way L1 cache way of the invalidated line affected by the eviction |
| 552 | * @param cycle issued time |
| 553 | */ |
| 554 | EvictInvCmd(uint32_t cid, |
| 555 | uint32_t srcBank, |
| 556 | uint32_t set, |
| 557 | uint32_t way, |
| 558 | uint64_t cycle); |
| 559 | }; |
| 560 | |
| 561 | class FetchIssueCmd : public LoadStoreCmd { |
| 562 | public: |
| 563 | /** |
| 564 | * A FetchIssue is issued when an instruction fetch is issued, every instruction |
| 565 | * should have one FetchIssue |
| 566 | * <p> |
| 567 | * @param itype fetch type associated with this command |
| 568 | * @param tid thread ID for the thread that issues this command |
| 569 | * @param id unique ID to identify this issue |
| 570 | * @param addr the address of the instruction to be fetched |
| 571 | * @param size size of the fetch |
| 572 | * @param cacheL1 boolean to determine if the access should be place in L1$ |
| 573 | * @param cycle issued time |
| 574 | */ |
| 575 | FetchIssueCmd(enum INSTR_TYPE itype, |
| 576 | uint32_t tid, |
| 577 | uint64_t id, |
| 578 | uint64_t addr, |
| 579 | uint8_t size, |
| 580 | bool cacheL1, |
| 581 | uint64_t cycle); |
| 582 | }; |
| 583 | |
| 584 | class FetchDataCmd : public LoadStoreCmd { |
| 585 | public: |
| 586 | /** |
| 587 | * A FetchData is issued when a fetch gets its data |
| 588 | * <p> |
| 589 | * @param tid thread ID for the thread that issues this command |
| 590 | * @param id unique ID to identify the FetchIssue corresponding to this FetchData |
| 591 | * @param addr the address where the instruction is fetched |
| 592 | * @param size size of the fetch |
| 593 | * @param dsrc data source, either from L1, IO, or L2/Memory |
| 594 | * @param cacheL1 boolean to determine if the access should be place in L1$ |
| 595 | * @param cycle issued time |
| 596 | */ |
| 597 | FetchDataCmd(uint32_t tid, |
| 598 | uint64_t id, |
| 599 | uint64_t addr, |
| 600 | uint8_t size, |
| 601 | enum DATA_SRC dsrc, |
| 602 | bool cacheL1, |
| 603 | uint64_t cycle); |
| 604 | }; |
| 605 | |
| 606 | class FetchFillCmd : public LoadStoreCmd { |
| 607 | public: |
| 608 | /** |
| 609 | * A FetchFill is issued when a fetched line is filled into L1 I$ and the |
| 610 | * new instruction can be seen by next access from the same core |
| 611 | * <p> |
| 612 | * @param tid thread ID for the thread whose fetch results in this line fill |
| 613 | * @param id unique ID to identify the fetch resulting in this line fill |
| 614 | * @param addr the address where the data is written |
| 615 | * @param cycle issued time |
| 616 | */ |
| 617 | FetchFillCmd(uint32_t tid, |
| 618 | uint64_t id, |
| 619 | uint64_t addr, |
| 620 | uint64_t cycle); |
| 621 | }; |
| 622 | |
| 623 | class DmaStoreCmd : public LoadStoreCmd { |
| 624 | public: |
| 625 | /** |
| 626 | * A DmaStoreCmd is issued when a dma_store command is issued, it is |
| 627 | * treated almost like a mem_slam, but with inv_vec to handle L1 conflict. |
| 628 | * <P> |
| 629 | * @param tid thread ID for the thread that issues this command |
| 630 | * @param id unique ID to identify this issue |
| 631 | * @param addr the address where the data is written |
| 632 | * @param data the data to be written |
| 633 | * @param size_vector valid byte mask of the data |
| 634 | * @param inv L1 cache invalidation vector |
| 635 | * @param tsize total data size of the DMA_STORE |
| 636 | * @param cycle issued time |
| 637 | */ |
| 638 | DmaStoreCmd(uint32_t tid, |
| 639 | uint64_t id, |
| 640 | uint64_t addr, |
| 641 | uint64_t data, |
| 642 | uint8_t size_vector, |
| 643 | uint32_t inv, |
| 644 | int tsize, |
| 645 | uint64_t cycle); |
| 646 | }; |
| 647 | |
| 648 | |
| 649 | #endif /* RIESLING_LOADSTORECMD_H */ |