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* OpenSPARC T2 Processor File: LoadStoreCmd.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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/************************************************************************
** Copyright (C) 2002, Sun Microsystems, Inc.
** Sun considers its source code as an unpublished, proprietary
** trade secret and it is available only under strict license provisions.
** This copyright notice is placed here only to protect Sun in the event
** the source is deemed a published work. Disassembly, decompilation,
** or other means of reducing the object code to human readable form
** is prohibited by the license agreement under which this code is
** provided to the user or company in possession of this copy."
*************************************************************************/
#include "MemorySyncDefs.h"
#include "MemorySyncMessage.h"
#include "RieslingInterface.h"
LoadStoreCmd(enum MEM_CMD cmd
, enum INSTR_TYPE itype
, uint32_t cid
, uint32_t tid
,
uint32_t srcTid
, uint32_t srcBank
, uint32_t inv
, uint32_t set
,
uint32_t way
, uint64_t id
, uint64_t addr
, uint64_t data
, uint8_t size_vector
,
uint8_t size
, enum DATA_SRC dsrc
, bool cacheL1
, bool rmo
, bool l2hit
,
bool switchData
, bool ioaddr
, uint64_t cycle
);
* @param orig The LoadStoreCmd object to copy.
LoadStoreCmd( const LoadStoreCmd
&orig
);
* @param rhs The right hand side of the equality operator
* @return Return true if this objec and rhs are equal,
/* bool operator==( const LoadStoreCmd &rhs ) const; */
* @param rhs The right hand side of the assignment operator.
* @return The lvalue of the assignment.
/* const LoadStoreCmd & operator=( const LoadStoreCmd &rhs ); */
* Return a string representation of this LoadStoreCmd object.
std::string
toString() const;
* This method initialize ioaddr_, rmoStore_, and rtlCycle variables
* Convert size to byte mask, maximum data is assumed 8 bytes
* @param size data size in the unit of byte
* @param aoffset 3 bits address offset
* @return 8 bit size mask in which bit0->byte0, bit1->byte1, etc <br>
* and a bit = 1 => the corresponding byte is valid
uint8_t sz2szv (uint8_t size
, uint32_t aoffset
);
* Convert 8 bits byte mask to size
* @param szv byte mask with bit0->byte0, bit1->byte1, etc, and <br>
* a bit = 1 => the corresponding byte is valid
* @return data size in the unit of byte, if a non-consecutive pattern of 1s <br>
* is in the szv, then always return 8
uint8_t szv2sz (uint8_t szv
);
* Convert the size to log2 notation
* @param size data size in the unit of byte
* @return the equivalent log2 representation
uint8_t sz2szlog (uint8_t size
);
/******************************************************************************
* General variables access methods
******************************************************************************/
enum MEM_CMD
getCmd() const { return cmd_
;}
enum INSTR_TYPE
getItype() const { return itype_
; }
enum DATA_SRC
getDsrc() const { return dsrc_
; }
bool isCacheL1() const { return cacheL1_
; }
bool isIO() const { return ioaddr_
; }
bool isRMOstore() const { return rmoStore_
; }
bool isL2hit() const { return l2hit_
; }
bool isSwitchData() const { return switchData_
; }
uint32_t getCoreId() const { return cid_
; }
uint32_t getThrdId() const { return tid_
; }
uint32_t getSrcTid() const { return srcTid_
; }
uint32_t getSrcBank() const { return srcBank_
; }
uint32_t getInv() const { return inv_
; }
uint32_t getSet() const { return set_
; }
uint32_t getWay() const { return way_
; }
uint64_t getCycle() const { return cycle_
; }
uint64_t getAddr() const { return addr_
; }
uint64_t getId() const { return id_
; }
uint64_t getData() const { return data_
; }
uint8_t getVbyte() const { return vbyte_
; }
uint8_t getSizeV() const { return vbyte_
; }
uint8_t getSize() const { return size_
; }
int getTsize() { return tsize
; }
void setCmd (enum MEM_CMD cmd
) { cmd_
= cmd
; }
void setItype (enum INSTR_TYPE itype
) { itype_
= itype
; }
void setDsrc (enum DATA_SRC dsrc
) { dsrc_
= dsrc
; }
void setCacheL1 (bool cacheL1
) { cacheL1_
= cacheL1
; }
void setIOaddr (bool ioaddr
) { ioaddr_
= ioaddr
; }
void setL2hit (bool l2hit
) { l2hit_
= l2hit
; }
void setRMOStore (bool rmoStore
) { rmoStore_
= rmoStore
; }
void setSwitchData (bool switchData
) { switchData_
= switchData
; }
void setCoreId (uint32_t cid
) { cid_
= cid
; }
void setThrdId (uint32_t tid
) { tid_
= tid
; }
void setSrcTid (uint32_t srcTid
) { srcTid_
= srcTid
; }
void setSrcBank (uint32_t srcBank
) { srcBank_
= srcBank
; }
void setInv (uint32_t inv
) { inv_
= inv
; }
void setSet (uint32_t set
) { set_
= set
; }
void setWay (uint32_t way
) { way_
= way
; }
void setCycle (uint64_t cycle
) { cycle_
= cycle
; }
void setAddr (uint64_t addr
) { addr_
= addr
; }
void setId (uint64_t id
) { id_
= id
; }
void setData (uint64_t data
) { data_
= data
; }
void setVbyte (uint8_t vbyte
) { vbyte_
= vbyte
; }
void setSizeV (uint8_t sizeV
) { vbyte_
= sizeV
; }
void setSize (uint8_t size
) { size_
= size
; }
void setTsize(int _tsize
) { tsize
= _tsize
; }
* See MemorySyncDefs.h for enum types of MEM_CMD, INSTR_TYPE, and DATA_SRC.
* cmd_ is the command type associated with the MemorySync APIs
enum MEM_CMD cmd_
; // memory operation command
* itype_ is the instruction type
enum INSTR_TYPE itype_
; // instruction type
* dsrc_ is the data source
enum DATA_SRC dsrc_
; // data source
* cacheL1_ indicates if the data needs to be cached in L1
bool cacheL1_
; // true: data to be cached in L1; false: otherwise
* ioaddr_ indicates if the access is to I/O address space
bool ioaddr_
; // true: I/O address range; false: otherwise
* rmoStore_ is to indicates if a store is a RMO store.
* The term RMO store is borrowed from Niagara. It means a store that does not
* perform dependence check and follows RMO memory consistency model. This type
* of stores includes Block Store and BLK_INIT store.
* In N2, a RMO store is removed from the store buffer when it is issued from
* the store buffer. Other types of stores will remain in the store buffer after
* its data is committed to the memory hierarchy (this is a simple approach to
* comply with TSO). Hence, the StoreAck of a RMO store is issued before its
* Storecommit; while the StoreAck of other type of store is issued after its
* Storecommit. In addition, although StoreAcks of a sequence of RMO stores
* remain in order, a non-RMO following an RMO could get out of order.
bool rmoStore_
; // true: the store is a RMO store; false: otherwise
* l2hit_ indicates a reference hits L2 or not.
* In general, the Memory Sync model does not care whether an access is L2 hit
* or not. The l2hit_ boolean defined here is for special cases.
* One example is the BLK_INIT store defined in Niagara 1 and 2. The behavior
* of this type of store also depends on whether it hits L2 or not. Normally,
* this is just another RMO store. However, if the following 3 conditions are
* satisfied, then the addressed 64-byte chunk becomes 0 before the store data
* - the 6 least significant bits of the address are 0,
* - the address is not within I/O address space, and
* - the acecss is not L2 hit
bool l2hit_
; // true: the access hits L2; false: otherwise
* switchData_ indicates if the memory data will be changed for an atomic instruction.
* Atomic instruction consists of two parts: load and store. However, for CAS
* instruction, if the comparison is a false, then the value of the addressed
* memory is not changed. In this case, Riesling won't send a store transaction
* to the memory, thus no store side callback. The switchData_ is false only if
* the atomic instruction is a CAS and its comparsion results in a false.
/******************************************************************************
* In Memory Sync Model notation, a core is an entity that contains L1 cache.
* Threads that share the same L1 cache belong to the same core.
******************************************************************************/
uint32_t cid_
; // core id
* tid_ is the flat thread id. <br>
* If a core has n threads, then the tid_ of core 0 will be in [0, n-1],
* the tid_ of core 1 will be in [n, 2n-1], and so on
uint32_t tid_
; // (global) thread id
* srcTid_ indicates the source thread that initiates an event, e.g., StoreInv
uint32_t srcTid_
; // source thread id that trigger this event, used in STORE_INV
* srcBank_ is the bank that initiates an event, e.g., EVICT
uint32_t srcBank_
; // source bank id where the event occurs, used in EVICT
* inv_ is L1 cache invalidation vector that reflects the directory info of
* a L2 cache line. Each bit corresponds a core: bit 0 -> core 0, bit 1 ->
* core 1, and so on. That a bit is 1 indicates the cache line exists in the
* corresponding core. The least significant bits of inv_ are used for D$;
* and the most significant bits are used for I$.
uint32_t inv_
; // L1 cache invalidation vector, bit0 -> core0, bit1 -> core1, etc.
uint32_t set_
; // set of a cache
* way_ is the way info of a cache
uint32_t way_
; // way of a cache
* addr_ is the physical address
uint64_t addr_
; // address
* The id_ field is to be used in out-of-order environment so that commands can
* be mapped with LoadIssue/StoreIssue. In the in-order environment, where load
* and store mostly follow some in-order rules, this field is not used.
* Niagara 1 and Niagara 2 do not use this field.
uint64_t id_
; // unique number for matching other mem_cmd for the same instr.
* cycle_ is the RTL cycle when the command happens.
uint64_t cycle_
; // the RTL cycle when the command happens
* data_ is the data for the memory operation
* The data format MemorySync model expects on STOREs is as follows: (Big Edian)
* +--------+--------+------------+--------+<br>
* data | byte 0 | byte 1 | --- | byte 7 |<br>
* (64 bits) +--------+--------+------------+--------+<br>
* size_vector: bit 7 bit 6 bit 0<br>
* vbyte_ is the byte mask as shown in the description of data_
uint8_t vbyte_
; // valid byte mask bit0 -> byte0, bit1 -> byte1, and so on
uint8_t size_
; // size of data
* used in DMA_STORE, a DMA_STORE operation can be 8 bytes or 64 bytes,
* testbench will break it into 8 byte per DMA_STORE command, we use the
* totla_size to calculate how many DMA_STORE commands are to be expected,
* the information is also used to handle related EVICT and EVICT_INV, as
* there will be only one EVICT for each DMA_STORE operation (meaning even
* if it is a 64-byte store, we will only see one EVICT).
class StoreIssueCmd
: public LoadStoreCmd
{
* A StoreIssueCmd is issued when a store is inserted into the store buffer
* after address translation
* @param itype instruction type associated with this command
* @param tid thread ID for the thread that issues this command
* @param id unique ID to identify this issue
* @param addr the address where the data is written
* @param data the data to be written
* @param size_vector valid byte mask of the data
* @param cycle issued time
StoreIssueCmd(enum INSTR_TYPE itype
,
class StoreCommitCmd
: public LoadStoreCmd
{
* A StorecommitCmd is issued when a store whose data is observed in L2
* (L2 is shared and is writeback in this model) by other thread/cpu
* @param tid thread ID for the thread that issues this command
* @param inv L1 cache invalidation vector
* @param id unique ID to identify the StoreIssue corresponding to this StoreCommit
* @param addr the address where the data is written
* @param size_vector this field can be valid byte mask of the data or comparison
* result of a CAS instruction where 0 means false comparison
* @param l2hit the store hit L2$ that is only used to handle BLK_INIT store
* @param cycle issued time
StoreCommitCmd(uint32_t tid
,
class StoreInvCmd
: public LoadStoreCmd
{
* A StoreInv is issued when an invalidation is performed on its L1 cache
* @param cid core ID that sees this invalidation
* @param srcTid thread ID that triggers this invalidation
* @param addr the address where the data is written
* @param cycle issued time
StoreInvCmd(uint32_t cid
,
class StoreUpdateCmd
: public LoadStoreCmd
{
* A StoreUpdate is issued when a update is performed on its L1 cache
* @param tid Thrd ID whose store results in this store update
* @param addr the address where the data is written
* @param cycle issued time
StoreUpdateCmd(uint32_t tid
,
class StoreAckCmd
: public LoadStoreCmd
{
* A StoreAck is issued when a store is removed from the store buffer
* Stores will be checked to see if they are Acked in order. Non-RMO
* stores and RMO stores are checked separately since although they
* should be Acked in order in each group, they can be out-of-order
* @param tid Thrd ID which sees the store ack
* @param addr the address where the data is written, always 0 in N2
* @param rmoStore indicates if the store is a RMO store
* @param cycle issued time
StoreAckCmd(uint32_t tid
,
class LoadIssueCmd
: public LoadStoreCmd
{
* A LoadIssue is issued when in RTL a load is issued from an in-order domain to
* @param itype instruction type associated with this command
* @param tid thread ID for the thread that issues this command
* @param id unique ID to identify this issue
* @param addr the address of the data to be loaded
* @param size size of to be loaded data
* @param cacheL1 boolean to determine if the load access should be place in L1$
* @param cycle issued time
LoadIssueCmd(enum INSTR_TYPE itype
,
class LoadDataCmd
: public LoadStoreCmd
{
* A LoadData is issued when a load gets its data
* @param tid thread ID for the thread that issues this command
* @param id unique ID to identify the LoadIssue corresponding to this LoadData
* @param addr the address where the data is loaded
* @param size size of to be loaded data
* @param dsrc data source, either from L1, STB, or L2/Memory
* @param cacheL1 boolean to determine if the load access should be place in L1$
* @param cycle issued time
LoadDataCmd(uint32_t tid
,
class LoadFillCmd
: public LoadStoreCmd
{
* A LoadFill is issued when a line is filled into L1 and the new data can be
* seen by next access from the same core
* @param tid thread ID for the thread whose load results in this line fill
* @param id unique ID to identify the load resulting in this line fill
* @param addr the address where the data is written
* @param cycle issued time
LoadFillCmd(uint32_t tid
,
class EvictCmd
: public LoadStoreCmd
{
* An Evict is issued When a line is evicted from L2 which will in turn
* invalid line in L1. A L2 line eviction may cause invalidation of
* multiple L1 lines. The MemorySync expects one Evict packet for each
* L1 cache line since each cache line may have different invalidation
* @param inv L1 cache invalidation vector
* @param set L1 cache set of the evicted line
* @param way L1 cache way of the evicted line
* @param addr the address of the evict line
* @param cycle issued time
class EvictInvCmd
: public LoadStoreCmd
{
* A EvictInv is issued when an invalidation is performed on its L1 cache
* @param cid core ID that sees this invalidation
* @param srcBank bank ID that triggers this invalidation
* @param set L1 cache set of the invalidated line affected by the eviction
* @param way L1 cache way of the invalidated line affected by the eviction
* @param cycle issued time
EvictInvCmd(uint32_t cid
,
class FetchIssueCmd
: public LoadStoreCmd
{
* A FetchIssue is issued when an instruction fetch is issued, every instruction
* should have one FetchIssue
* @param itype fetch type associated with this command
* @param tid thread ID for the thread that issues this command
* @param id unique ID to identify this issue
* @param addr the address of the instruction to be fetched
* @param size size of the fetch
* @param cacheL1 boolean to determine if the access should be place in L1$
* @param cycle issued time
FetchIssueCmd(enum INSTR_TYPE itype
,
class FetchDataCmd
: public LoadStoreCmd
{
* A FetchData is issued when a fetch gets its data
* @param tid thread ID for the thread that issues this command
* @param id unique ID to identify the FetchIssue corresponding to this FetchData
* @param addr the address where the instruction is fetched
* @param size size of the fetch
* @param dsrc data source, either from L1, IO, or L2/Memory
* @param cacheL1 boolean to determine if the access should be place in L1$
* @param cycle issued time
FetchDataCmd(uint32_t tid
,
class FetchFillCmd
: public LoadStoreCmd
{
* A FetchFill is issued when a fetched line is filled into L1 I$ and the
* new instruction can be seen by next access from the same core
* @param tid thread ID for the thread whose fetch results in this line fill
* @param id unique ID to identify the fetch resulting in this line fill
* @param addr the address where the data is written
* @param cycle issued time
FetchFillCmd(uint32_t tid
,
class DmaStoreCmd
: public LoadStoreCmd
{
* A DmaStoreCmd is issued when a dma_store command is issued, it is
* treated almost like a mem_slam, but with inv_vec to handle L1 conflict.
* @param tid thread ID for the thread that issues this command
* @param id unique ID to identify this issue
* @param addr the address where the data is written
* @param data the data to be written
* @param size_vector valid byte mask of the data
* @param inv L1 cache invalidation vector
* @param tsize total data size of the DMA_STORE
* @param cycle issued time
DmaStoreCmd(uint32_t tid
,
#endif /* RIESLING_LOADSTORECMD_H */