Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_DramFbdInjectedErrSrcReg.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="DRAM_FBD_INJ_ERROR_SRC_REG (DRAM_FBD_INJ_ERROR_SRC_REG)">
   <class_name>N2_DramFbdInjectedErrSrcReg</class_name>
   <submodule>N2</submodule>
   <comment>
DRAM FBD Injected Error Source Register. When the NCU siganls the MCU
to inject an error, this register determines into which error
detection logic the error will be injected.
TABLE 12-38 shows the format of the DRAM FDB Injected Error Source
Register. TABLE 12-38 FBD Error Syndrome Register - DRAM_FBD_INJ_ERROR_SRC_REG (0x84-0000-0c08) (Count 4 Step 4096)
   </comment>
   <base_address>0x8400000c08ULL</base_address>
   <count>4</count>
   <stride>4096</stride>
   <priv>yes</priv>
   <public>
   static const uint_t CRC_ERROR = 0;
   static const uint_t ALERT_FRAME_ERROR = 1;
   static const uint_t ALERT_ASSERTED = 2;
   static const uint_t STATUS_FRAME_PARITY_ERROR = 3;
   </public>
   <field name="RSVD0">
       <start_offset>2</start_offset>
       <end_offset>62</end_offset>
       <initial_value>0</initial_value>
       <protection>RO</protection>
       <field_type>ZERO</field_type>
       <comment>
Reserved
       </comment>
   </field>
   <field name="ERRORSOURCE">
       <start_offset>0</start_offset>
       <end_offset>1</end_offset>
       <initial_value>0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
Source of the Error.
0: CRC Error
1: Alert Frame Error
2: Alert Asserted
3: Status Frame Parity Error
       </comment>
       <format type="hex"/>
   </field>
</register>
</register_list>