Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_L2ErrorEnMem.xml

<!-- interpreter=xml2reg args='-t' -->
<register_list>
<register name="L2_ERROR_EN_REG (L2_ERROR_EN_REG)">
   <class_name>N2_L2ErrorEnMem</class_name>
   <submodule>N2</submodule>
   <comment>
Each L2 bank has an error enable register which controls the reporting of L2 errors for that bank back to the initiator of an operation (or to the virtual core specified in L2_CSR_REG.ERRORSTEER if no initiator exists or can be readily identified). The L2 Error Enable Register, the format of which is shown in TABLE 12-20, is available at address 0xAA-0000-0000 or 0xBA-0000-0000. Address bits 8:6 select the cache bank, address bits 31:9 and 5:3 are ignored (i.e. the register aliases across the address range). Error Enable Register - L2_ERROR_EN_REG (0xAA-0000-0000) (Count 8 Step 64).
   </comment>
   <base_address>0xAA00000000ULL</base_address>
   <count>8</count>
   <stride>64</stride>
   <priv>yes</priv>
   <field name="CEEN">
       <start_offset>0</start_offset>
       <end_offset>0</end_offset>
       <initial_value>0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
If set to 1, report correctable errors.
       </comment>
       <format type="hex"/>
   </field>
   <field name="NCEEN">
       <start_offset>1</start_offset>
       <end_offset>1</end_offset>
       <initial_value>0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
If set to 1, report uncorrectable errors.
       </comment>
       <format type="hex"/>
   </field>
   <field name="DEBUG_TRIG_EN">
       <start_offset>2</start_offset>
       <end_offset>2</end_offset>
       <initial_value>0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
Trigger enable for the debug port.
       </comment>
       <format type="hex"/>
   </field>
   <field name="RSVD0">
       <start_offset>3</start_offset>
       <end_offset>63</end_offset>
       <initial_value>0</initial_value>
       <protection>RO</protection>
       <field_type>ZERO</field_type>
       <comment>
Reserved
       </comment>
   </field>
</register>
</register_list>