Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_SocErrorInjectReg.xml

<!-- interpreter=xml2reg args='-t'-->
<register_list>
<register name="SOC_ERROR_INJECTION_REG (SOC_ERROR_INJECTION_REG)">
   <class_name>N2_SocErrorInjectReg</class_name>
   <submodule>N2</submodule>
   <comment>
SOC Error Injection Register. This register controls the injection of
errors.  The valid bit of this register must be set to 1 for aany
error injection.  If the valid bit is set to 1, continuous errors are
generated for any error types with their bit set in the register.
TABLE 12-56 shows the format of the SOC Error Injection Register. TABLE 12-56
SOC Error Injection Register - SOC_ERROR_INJECTION_REG (0x80-0000-3018)
   </comment>
   <inherits>n2/lib/ras/xml/N2_SocErrorReg.xml</inherits>
   <base_address>0x8000003018ULL</base_address>
   <count>1</count>
   <stride>8</stride>
   <priv>yes</priv>
   <field name="V">
       <start_offset>63</start_offset>
       <end_offset>63</end_offset>
       <initial_value>0</initial_value>
       <protection>RW</protection>
       <field_type>NORMAL</field_type>
       <comment>
Multiple uncorrected errors, one or more uncorrected errors were not logged.
       </comment>
       <format type="hex"/>
   </field>
</register>
</register_list>