Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / n2 / lib / ras / xml / N2_SocErrorIntrEnReg.xml

<!-- interpreter=xml2reg args='-t'-->
<register_list>
<register name="SOC_ERROR_INTERRUPT_ENABLE_REG (SOC_ERROR_INTERRUPT_ENABLE_REG)">
   <class_name>N2_SocErrorIntrEnReg</class_name>
   <submodule>N2</submodule>
   <comment>
SOC Error Interrupt Enable Register. This register controls which
errors will generate an Error Indication (SOC) error packet to the
CPX.  If the EIE bit is set, an Error Indication (SOC) error packet
will always be sent to the CPX irrespective of whether the error
caused the transaction to be terminated or not.  The Correctable SOC
errors will set an error code of 0b'01' in the error field of the
packaet with uncorrectable SOC errors set an error code of 0b'10' in
the error field.  TABLE 12-52 shows the format of the SOC Error Interrupt Enable Register. TABLE 12-52
SOC Error Interrupt Enable Register - SOC_ERROR_INTERRUPT_ENABLE_REG (0x80-0000-3010)
   </comment>
   <inherits>n2/lib/ras/xml/N2_SocErrorReg.xml</inherits>
   <base_address>0x8000003010ULL</base_address>
   <count>1</count>
   <stride>8</stride>
   <priv>yes</priv>
   <field name="DUMMY1">
       <start_offset>63</start_offset>
       <end_offset>63</end_offset>
       <initial_value>0</initial_value>
       <protection>RO</protection>
       <field_type>ZERO</field_type>
       <comment>
Unused.
       </comment>
       <format type="hex"/>
   </field>
</register>
</register_list>