Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / dev / ram / src / SS_Ram.cc

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: SS_Ram.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================

#include <sys/socket.h>
#include <unistd.h>
#include "SS_Ram.h"

SS_Ram::SS_Ram( SS_AddressMap* map, SS_Paddr lo, SS_Paddr hi )/*{{{*/
:
 base(lo),
 ram(&SS_Memory::memory)
{
 map->add(lo,hi,this,SS_AddressMap::REL,SS_Ram::access);
}
/*}}}*/
SS_Ram::~SS_Ram()/*{{{*/
{
}
/*}}}*/

void SS_Ram::access( void* obj, uint_t sid, SS_Access::Type type, SS_Paddr pa, uint_t size, uint64_t* data )/*{{{*/
{
 SS_Ram* self = (SS_Ram*)obj;

 pa += self->base;

 switch (type)
 {
   case SS_Access::LOAD:
     switch (size)
     {
       case  1: *data = self->ram->ld8u(pa); break;
       case  2: *data = self->ram->ld16u(pa); break;
       case  4: *data = self->ram->ld32u(pa); break;
       case  8: *data = self->ram->ld64(pa); break;
       case 16: self->ram->ld128(pa,data); break;
       case 64: self->ram->ld512(pa,data); break;
       default: assert(0);
     }
     break;
   case SS_Access::STORE:
     switch (size)
     {
       case  1: self->ram->st8(pa,*data); break;
       case  2: self->ram->st16(pa,*data); break;
       case  4: self->ram->st32(pa,*data); break;
       case  8: self->ram->st64(pa,*data); break;
       case 16: self->ram->st128(pa,data); break;
       case 64: self->ram->st512(pa,data); break;
       default: assert(0);
     }
     break;
   case SS_Access::STP:
     assert(size == 8);
     self->ram->st64partial(pa,data[0],data[1]);
     break;
   case SS_Access::SWAP:
     assert(size == 4);
     *data = self->ram->swap(pa,*data);
     break;
   case SS_Access::LDST:
     assert(size == 1);
     *data = self->ram->ldstub(pa);
     break;
   case SS_Access::CAS:
     switch (size)
     {
       case  4: *data = self->ram->cas(pa,data[0],data[1]); break;
       case  8: *data = self->ram->casx(pa,data[0],data[1]); break;
       default: assert(0);
     }
     break;
   default:
     fprintf(stderr,"ROM: Invalid access detected\n");
     assert(0);
 }
}
/*}}}*/