sam-t2/sam/cpus/vonk/ss/lib/cpu/src/SS_Io.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: SS_Io.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
#ifndef __SS_Io_h__
#define __SS_Io_h__

#ifdef COMPILE_FOR_SAM

#include "SS_SamIo.h"

#else

#ifndef MEMORY_MSYNC

#include "SS_Types.h"
#include "SS_AddressMap.h"

class SS_Io : public SS_AddressMap/*{{{*/
{
  public:
    SS_Io();
    ~SS_Io();

    enum access_io_status {
        NOT_HANDLED=-1,
        OK=0,
        FOLLOWME=1,
        NOP=2,
        RSVD_READ=3, // read from reserved range
        RSVD_WRITE=4 // write to reserved range
    };

    // Supported User Interface Operations

    void     poke8 (  uint_t sid,uint64_t addr, uint8_t  data )         { st8(sid,addr,data); }
    void     poke16(  uint_t sid, uint64_t addr, uint16_t data )        { st16(sid,addr,data); }
    void     poke32(  uint_t sid,uint64_t addr, uint32_t data )         { st32(sid,addr,data); }
    void     poke64(  uint_t sid,uint64_t addr, uint64_t data )         { st64(sid,addr,data); }
    uint8_t  peek8u(  uint_t sid,uint64_t addr )                                { return ld8u(sid,addr); }
     int8_t  peek8s(  uint_t sid,uint64_t addr )                                { return ld8s(sid,addr); }
    uint16_t peek16u( uint_t sid,uint64_t addr )                                { return ld16u(sid,addr); }
     int16_t peek16s( uint_t sid,uint64_t addr )                                { return ld16s(sid,addr); }
    uint32_t peek32u( uint_t sid,uint64_t addr )                                { return ld32u(sid,addr); }
     int32_t peek32s( uint_t sid,uint64_t addr )                                { return ld32s(sid,addr); }
    uint64_t peek64(  uint_t sid,uint64_t addr )                                { return ld64(sid,addr); }

    // Supported Fetch Operation (instruction fetch)

    uint32_t fetch32( uint_t sid, uint64_t addr )                       { return ld32u(sid,addr); }
    void     fetch256( uint_t sid, uint64_t addr, uint64_t data[4] )    { ld256(sid,addr,data); }
    void     fetch512( uint_t sid, uint64_t addr, uint64_t data[8] )    { ld512(sid,addr,data); }

    // Supported Store Operations. st8(), st16(), st32() and st64() are gueranteed to be atomic.
    // st128() and st512() are atomic at the 64bit granularity.

    void st8  ( uint_t sid, uint64_t addr, uint8_t data );
    void st16 ( uint_t sid, uint64_t addr, uint16_t data );
    void st32 ( uint_t sid, uint64_t addr, uint32_t data );
    void st64 ( uint_t sid, uint64_t addr, uint64_t data );
    void st128( uint_t sid, uint64_t addr, uint64_t data[2] );
    void st512( uint_t sid, uint64_t addr, uint64_t data[8] );

    // Supported Load Operations. ld8[su]() to ld64() are quaranteed to be atomic. ld128() and
    // above are atomic at the 64 bit granularity.

    uint8_t  ld8u ( uint_t sid, uint64_t addr );
     int8_t  ld8s ( uint_t sid, uint64_t addr );
    uint16_t ld16u( uint_t sid, uint64_t addr );
     int16_t ld16s( uint_t sid, uint64_t addr );
    uint32_t ld32u( uint_t sid, uint64_t addr );
     int32_t ld32s( uint_t sid, uint64_t addr );
    uint64_t ld64 ( uint_t sid, uint64_t addr );
    void     ld128( uint_t sid, uint64_t addr, uint64_t data[2] );
    void     ld256( uint_t sid, uint64_t addr, uint64_t data[4] );
    void     ld512( uint_t sid, uint64_t addr, uint64_t data[8] );

    // st64partial() performs 8 byte partial store. The bits to store are specified by mask. A 1 in bit N of
    // mask denotes that bit (data >> (N)) should be written.

    void st64partial( uint_t sid, uint64_t addr, uint64_t data, uint64_t mask );

    // ld128atomic() (aka load twin double, load quad atomic) atomically loads two
    // 64bit values from memory at addr into rd. rd[0] is the value at addr, rd[1]
    // is the value at addr + 8. Note ld128 does() not guarantee atomicity.

    void ld128atomic( uint_t sid, uint64_t addr, uint64_t data[2] );

    // ldstub() return a byte from memory at addr, and set the byte at addr
    // to 0xff. The ldstub() operation is atomic.

    uint8_t ldstub( uint_t sid, uint64_t addr );

    // swap() stores the 32bit value rd with the 32bit value at addr.
    // The old 32bit value at addr is returned.  The operation is atomic.

    uint32_t swap( uint_t sid, uint64_t addr, uint32_t rd );

    // casx() compares the 64bit value rs2 with the 64bit value at addr.
    // If the two values are equal, the value rd is stored in the
    // 64bit value at addr. In both cases the old 64bit value at addr is
    // returned, that is the value at addr before the storei happened.
    // The casx() operation is atomic.

    uint64_t casx( uint_t sid, uint64_t addr, uint64_t rd, uint64_t rs2 );

    // cas() is as casx, but for 32bit.

    uint32_t cas( uint_t sid, uint64_t addr, uint32_t rd, uint32_t rs2 );

    // prefetch() prefetches data from memory into the cache hierarchy.

    void prefetch( uint_t sid, uint64_t addr, uint_t size ) {}

    // flush() writes dirty data in the cache back to memory

    void flush( uint_t sid, uint64_t addr, uint_t size ) {}   // process does not provide data.

    static SS_Io io;
};
/*}}}*/

#else

#include <string.h>
#include <sys/mman.h>
#include "SS_Types.h"
#include "SS_AddressMap.h"
#include "SS_Memory.h"
#include "MemoryTransaction.h"

class SS_Io : public SS_AddressMap/*{{{*/
{
  public:
    SS_Io();
    ~SS_Io();

    enum access_io_status {
        NOT_HANDLED=-1,
        OK=0,
        FOLLOWME=1,
        NOP=2,
        RSVD_READ=3, // read from reserved range
        RSVD_WRITE=4 // write to reserved range
    };


    // Supported User Interface Operations

    void    poke8 ( int sid, uint64_t addr, uint8_t  data );
    void    poke16( int sid, uint64_t addr, uint16_t data );
    void    poke32( int sid, uint64_t addr, uint32_t data );
    void    poke64( int sid, uint64_t addr, uint64_t data );

    uint8_t  peek8u(  int sid, uint64_t addr );
    int8_t   peek8s(  int sid, uint64_t addr );
    uint16_t peek16u( int sid, uint64_t addr );
    int16_t  peek16s( int sid, uint64_t addr );
    uint32_t peek32u( int sid, uint64_t addr );
    int32_t  peek32s( int sid, uint64_t addr );
    uint64_t peek64(  int sid, uint64_t addr );

    // Supported Fetch Operation (instruction fetch)

    uint32_t fetch32( uint_t sid, uint64_t addr );
    void     fetch256( uint_t sid, uint64_t addr, uint64_t data[4] );
    void     fetch512( uint_t sid, uint64_t addr, uint64_t data[8] );

    // Supported Store Operations. st8(), st16(), st32() and st64() are gueranteed to be atomic.
    // st128() and st512() are atomic per 64bit quantity.

    void st8( uint_t sid, uint64_t addr, uint8_t data );
    void st16( uint_t sid, uint64_t addr, uint16_t data );
    void st32( uint_t sid, uint64_t addr, uint32_t data );
    void st64( uint_t sid, uint64_t addr, uint64_t data );
    void st128( uint_t sid, uint64_t addr, uint64_t data[2] );
    void st512( uint_t sid, uint64_t addr, uint64_t data[8] );

    // Supported Load Operations. ld8[su]() to ld64() are quaranteed to be atomic. ld128() and
    // above are atomic at the 64 bit granularity.

    uint8_t  ld8u ( uint_t sid, uint64_t addr );
    int8_t   ld8s( uint_t sid, uint64_t addr );
    uint16_t ld16u( uint_t sid, uint64_t addr );
    int16_t  ld16s( uint_t sid, uint64_t addr );
    uint32_t ld32u( uint_t sid, uint64_t addr );
    int32_t  ld32s( uint_t sid, uint64_t addr );
    uint64_t ld64( uint_t sid, uint64_t addr );
    void     ld128( uint_t sid, uint64_t addr, uint64_t data[2] );
    void     ld256( uint_t sid, uint64_t addr, uint64_t data[4] );
    void     ld512( uint_t sid, uint64_t addr, uint64_t data[8] );

    // st64partial() performs 8 byte partial store. The bytes to store are specified by mask. A 1 in bit N of
    // mask denotes that byte (data >> (8*N)) & 0xff should be written to memory

    void st64partial( uint_t sid, uint64_t addr, uint64_t data, uint64_t mask );

    // ld128atomic() (aka load twin double, load quad atomic) atomically loads two
    // 64bit values from memory at addr into rd. rd[0] is the value at addr, rd[1]
    // is the value at addr + 8. Note ld128 does() not guarantee atomicity.

    void ld128atomic( uint_t sid, uint64_t addr, uint64_t data[2] );

    // ldstub() return a byte from memory at addr, and set the byte at addr
    // to 0xff. The ldstub() operation is atomic.

    uint8_t ldstub( uint_t sid, uint64_t addr );

    // swap() stores the 32bit value rd with the 32bit value at addr.
    // The old 32bit value at addr is returned.  The operation is atomic.

    uint32_t swap( uint_t sid, uint64_t addr, uint32_t rd );

    // casx() compares the 64bit value rs2 with the 64bit value at addr.
    // If the two values are equal, the value rd is stored in the
    // 64bit value at addr. In both cases the old 64bit value at addr is
    // returned, that is the value at addr before the storei happened.
    // The casx() operation is atomic.

    uint64_t casx( uint_t sid, uint64_t addr, uint64_t rd, uint64_t rs2 );

    // cas() is as casx, but for 32bit.

    uint32_t cas( uint_t sid, uint64_t addr, uint32_t rd, uint32_t rs2 );

    // prefetch() prefetches data from memory into the cache hierarchy.

    void prefetch( uint_t sid, uint64_t addr, uint_t size ) {}

    // flush() writes dirty data in the cache back to memory

    void flush( uint_t sid, uint64_t addr, uint_t size ) {}   // process does not provide data.

    static SS_Io io;

    //----------------------------------------------------------------------------
    // Memory Sync additional interface
    //----------------------------------------------------------------------------

    void msync_info( uint_t strand_id, SS_Vaddr va, SS_Memory::Info info=SS_Memory::NONE )
    {
      mem_xact.setStrand(strand_id);
      mem_xact.vaddr(va);
      msync_help = info;
    }

    void*  msync_object;
    void (*msync_pre_access)( void* object, MemoryTransaction& );
    void (*msync_post_access)( void* object, MemoryTransaction& );

    typedef int (*AccessIO)( void* obj, int sid, int type, uint64_t addr, uint32_t size, uint64_t* data, uint64_t bitmask);

    void set_access_io( AccessIO _access_io )   { access_io = _access_io; }

    void set_access_io_obj( void* access_obj )  { access_io_obj = access_obj; }

    void peek128( int sid, uint64_t addr ,uint64_t data[2] );
    void peek256( int sid, uint64_t addr ,uint64_t data[4] );
    void peek512( int sid, uint64_t addr ,uint64_t data[8] );
    void poke128( int sid, uint64_t addr, uint64_t data[2] );
    void poke512( int sid, uint64_t addr, uint64_t data[8] );

  private:
    SS_Memory*        memory;
    MemoryTransaction mem_xact;
    SS_Memory::Info   msync_help;
    AccessIO          access_io;
    void *access_io_obj;

    uint64_t msync_ld( int sid, uint64_t addr, uint_t size );
    void     msync_ld( int sid, uint64_t addr, uint_t size, uint64_t* data );
    void     msync_st( int sid, uint64_t addr, uint_t size, uint64_t data );
    void     msync_st( int sid, uint64_t addr, uint_t size, uint64_t* data );
};
/*}}}*/

#endif /* MEMORY_MSYNC */
#endif /* COMPILE_FOR_SAM */
#endif /* __SS_Io_h__ */