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* Hypervisor Software File: ldc.h
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#pragma ident "@(#)ldc.h 1.3 07/05/17 SMI"
* Location of the SRAM queues
* XXX - Eventually, we probably want to read this out of the SRAM.
* For now it is hardcoded between HV and vbsc.
#define LDC_SRAM_CHANNEL_TXBASE FPGA_BASE + FPGA_SRAM_BASE + 0x460
#define LDC_SRAM_CHANNEL_RXBASE FPGA_BASE + FPGA_SRAM_BASE + 0x19a0
#define FPGA_LDCIN_BASE FPGA_Q1IN_BASE
#define FPGA_LDCOUT_BASE FPGA_Q1OUT_BASE
#define FPGA_LDC_RECV_REG 0x0
#define FPGA_LDC_MASK_REG 0x10
* FPGA_LDC_RECV_REG[14:0] space available for channel
* FPGA_LDC_RECV_REG[30:16] data available for channel
* bit[15] unused, reserved for future use
* FPGA_LDC_RECV_REG[31] reset all channels
#define FPGA_LDC_RECV_TX_CHANNELS 15
#define FPGA_LDC_RECV_TX_CHANNEL_MASK 0x7fff
#define FPGA_LDC_RECV_TX_CHANNEL_SHIFT 0
#define FPGA_LDC_RECV_RX_CHANNELS 30
#define FPGA_LDC_RECV_RX_CHANNEL_MASK 0x7fff0000
#define FPGA_LDC_RECV_RX_CHANNEL_SHIFT 16
#define FPGA_LDC_RECV_STATE_CHG_MASK 0x80000000 /* bit 31 */
* FPGA Interrupts for LDC
#define IRQ_LDC_OUT (IRQ1_QUEUE_OUT | IRQ1_QUEUE_IN)
* Send the SP an interrupt on the LDC IN channel.
* target_endpt target endpoint, preserved
* status_bit interrupt type
#define LDC_SEND_SP_INTR(target_endpt, tmp1, tmp2, status_bit) \
setx FPGA_LDCOUT_BASE, tmp1, tmp2 ;\
cmp tmp1, SP_LDC_STATE_CHG ;\
set FPGA_LDC_RECV_STATE_CHG_MASK, tmp1 ;\
ldub [target_endpt + LDC_CHANNEL_IDX], target_endpt ;\
add target_endpt, FPGA_LDC_RECV_TX_CHANNEL_SHIFT, target_endpt ;\
sllx tmp1, target_endpt, tmp1 ;\
add target_endpt, FPGA_LDC_RECV_RX_CHANNEL_SHIFT, target_endpt ;\
sllx tmp1, target_endpt, tmp1 ;\
st tmp1, [tmp2 + FPGA_LDC_RECV_REG] ;\
#ifdef CONFIG_SPLIT_SRAM_ERRATUM
typedef struct sp_ldc_sram_ptrs
{
uint64_t inq_data_offset
;
uint64_t inq_num_packets
;
uint64_t outq_data_offset
;
uint64_t outq_num_packets
;
#endif /* CONFIG_SPLIT_SRAM_ERRATUM */
#endif /* _PLATFORM_LDC_H */