[unix-history] / usr / src / sys / sparc / sbus / bwtworeg.h

/*
 * Copyright (c) 1992 The Regents of the University of California.
 * All rights reserved.
 *
 * This software was developed by the Computer Systems Engineering group
 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
 * contributed to Berkeley.
 *
 * All advertising materials mentioning features or use of this software
 * must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Lawrence Berkeley Laboratory.
 *
 * %sccs.include.redist.c%
 *
 *	@(#)bwtworeg.h	7.3 (Berkeley) %G%
 *
 * from: $Header: bwtworeg.h,v 1.4 92/11/26 02:28:05 torek Exp $
 */

/*
 * bwtwo display registers.
 *
 * The registers start at offset 0x400000 and repeat every 32 bytes
 * (presumably only the low order address lines are decoded).  Video RAM
 * starts at offset 0x800000.  We use separate pointers to each so that
 * the sparc addressing modes work well.
 */
struct bwtworeg {
	/*
	 * The xxx0 range is all 0xff on my IPC but causes a screen glitch
	 * on my SS1+, so it must do *some*thing... the xxx1 range is full
	 * of values but I do not know what they are.  bw_ctl changes for
	 * a blanked screen.
	 */
	char	bw_xxx0[16];
	u_char	bw_ctl;			/* contains video enable */
	char	bw_xxx1[15];
};

/* bits in bw_ctl */
#define	CTL_VE	0x40			/* video enable */

/* offsets */
#define	BWREG_ID	0
#define	BWREG_REG	0x400000
#define	BWREG_MEM	0x800000

/* same, but for gdb */
struct bwtwo_all {
	long	ba_id;			/* ID = 0xfe010104 on my IPC */
	char	ba_xxx0[0x400000-4];
	struct	bwtworeg ba_reg;	/* control registers */
	char	ba_xxx1[0x400000-32];
	char	ba_ram[4096];		/* actually larger */
};
Commit	Line	Data
1383b055 CT	1	/*
	2	* Copyright (c) 1992 The Regents of the University of California.
	3	* All rights reserved.
	4	*
	5	* This software was developed by the Computer Systems Engineering group
	6	* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
	7	* contributed to Berkeley.
	8	*
b480239a KB	9	* All advertising materials mentioning features or use of this software
	10	* must display the following acknowledgement:
	11	* This product includes software developed by the University of
1869bdc0	12	* California, Lawrence Berkeley Laboratory.
b480239a	13	*
1383b055 CT	14	* %sccs.include.redist.c%
1383b055 CT	15	*
1869bdc0	16	* @(#)bwtworeg.h 7.3 (Berkeley) %G%
1383b055	17	*
1869bdc0	18	* from: $Header: bwtworeg.h,v 1.4 92/11/26 02:28:05 torek Exp $
1383b055 CT	19	*/
	20
	21	/*
	22	* bwtwo display registers.
	23	*
	24	* The registers start at offset 0x400000 and repeat every 32 bytes
	25	* (presumably only the low order address lines are decoded). Video RAM
	26	* starts at offset 0x800000. We use separate pointers to each so that
	27	* the sparc addressing modes work well.
	28	*/
	29	struct bwtworeg {
	30	/*
	31	* The xxx0 range is all 0xff on my IPC but causes a screen glitch
	32	* on my SS1+, so it must do something... the xxx1 range is full
	33	* of values but I do not know what they are. bw_ctl changes for
	34	* a blanked screen.
	35	*/
	36	char bw_xxx0[16];
	37	u_char bw_ctl; /* contains video enable */
	38	char bw_xxx1[15];
	39	};
	40
	41	/* bits in bw_ctl */
	42	#define CTL_VE 0x40 /* video enable */
	43
	44	/* offsets */
	45	#define BWREG_ID 0
	46	#define BWREG_REG 0x400000
	47	#define BWREG_MEM 0x800000
	48
	49	/* same, but for gdb */
	50	struct bwtwo_all {
	51	long ba_id; /* ID = 0xfe010104 on my IPC */
	52	char ba_xxx0[0x400000-4];
	53	struct bwtworeg ba_reg; /* control registers */
	54	char ba_xxx1[0x400000-32];
	55	char ba_ram[4096]; /* actually larger */
	56	};