[unix-history] / usr / src / sys / vax / uba / ubavar.h

/*	ubavar.h	4.6	%G%	*/

/*
 * unibus adapter
 */
#if VAX750
#define	UBA750	((struct uba_regs *)0xf30000)
#define	UMEM750	((u_short *)0xfc0000)
#endif

#if VAX780
/*
 * UBA registers
 */
struct uba_regs
{
	int	uba_cnfgr;
	int	uba_cr;
	int	uba_sr;
	int	uba_dcr;
	int	uba_fmer;
	int	uba_fubar;
	int	pad1[2];
	int	uba_brsvr[4];
	int	uba_brrvr[4];
	int	uba_dpr[16];
	int	pad2[480];
	struct	pte uba_map[496];
	int	pad3[16];
};

/* UBA control register, UBACR */
#define	UBA_MRD16	0x40000000	/* map reg disable bit 4 */
#define	UBA_MRD8	0x20000000	/* map reg disable bit 3 */
#define	UBA_MRD4	0x10000000	/* map reg disable bit 2 */
#define	UBA_MRD2	0x08000000	/* map reg disable bit 1 */
#define	UBA_MRD1	0x04000000	/* map reg disable bit 0 */
#define	UBA_IFS		0x00000040	/* interrupt field switch */
#define	UBA_BRIE	0x00000020	/* BR interrupt enable */
#define	UBA_USEFIE	0x00000010	/* UNIBUS to SBI error field IE */
#define	UBA_SUEFIE	0x00000008	/* SBI to UNIBUS error field IE */
#define	UBA_CNFIE	0x00000004	/* configuration IE */
#define	UBA_UPF		0x00000002	/* UNIBUS power fail */
#define	UBA_ADINIT	0x00000001	/* adapter init */

/* UBA status register, UASR */
#define	UBA_BR7FULL	0x08000000	/* BR7 receive vector reg full */
#define	UBA_BR6FULL	0x04000000	/* BR6 receive vector reg full */
#define	UBA_BR5FULL	0x02000000	/* BR5 receive vector reg full */
#define	UBA_BR4FULL	0x01000000	/* BR4 receive vector reg full */
#define	UBA_RDTO	0x00000400	/* UNIBUS to SBI read data timeout */
#define	UBA_RDS		0x00000200	/* read data substitute */
#define	UBA_CRD		0x00000100	/* corrected read data */
#define	UBA_CXTER	0x00000080	/* command transmit error */
#define	UBA_CXTMO	0x00000040	/* command transmit timeout */
#define	UBA_DPPE	0x00000020	/* data path parity error */
#define	UBA_IVMR	0x00000010	/* invalid map register */
#define	UBA_MRPF	0x00000008	/* map register parity failure */
#define	UBA_LEB		0x00000004	/* lost error */
#define	UBA_UBSTO	0x00000002	/* UNIBUS select timeout */
#define	UBA_UBSSTO	0x00000001	/* UNIBUS slave sync timeout */

/* BR receive vector register, BRRVR */
#define	UBA_AIRI	0x80000000	/* adapter interrupt request */
#define	UBA_DIV		0x0000ffff	/* device interrupt vector field */
#endif
 
/* data path register, DPR */
#if VAX780
#define	UBA_BNE		0x80000000	/* buffer not empty - purge */
#define	UBA_BTE		0x40000000	/* buffer transfer error */
#define	UBA_DPF		0x20000000	/* DP function (RO) */
#define	UBA_BS		0x007f0000	/* buffer state field */
#define	UBA_BUBA	0x0000ffff	/* buffered UNIBUS address */
#endif
#if VAX750
#define	UBA_ERROR	0x20000000
#define	UBA_NXM		0x40000000
#define	UBA_UCE		0x20000000
#define	UBA_PURGE	0x00000001
#endif
 
/* map register, MR */
#define	UBA_MRV		0x80000000	/* map register valid */
#define	UBA_BO		0x02000000	/* byte offset bit */
#define	UBA_DPDB	0x01e00000	/* data path designator field */
#define	UBA_SBIPFN	0x000fffff	/* SBI page address field */

#define	UBA_DPSHIFT	21		/* shift to data path designator */

/*
 * Each UNIBUS mass storage controller has uba_minfo structure,
 * and a uba_dinfo structure (as below) for each attached drive.
 */
struct	uba_minfo {
	struct	uba_driver *um_driver;
	short	um_ctlr;	/* controller index in driver */
	short	um_ubanum;	/* the uba it is on */
	short	um_alive;	/* controller exists */
	int	(**um_intr)();	/* interrupt handler(s) */
	caddr_t	um_addr;	/* address of device in i/o space */
	struct	uba_info *um_forw;
	struct	uba_hd *um_hd;
	struct	buf um_tab;	/* queue for this controller */
};
/*
 * Each UNIBUS device has a uba_dinfo structure.
 * If a controller has many drives attached, then there will
 * be several uba_dinfo structures associated with a single uba_minfo
 * structure.
 */
struct	uba_dinfo {
	struct	uba_driver *ui_driver;
	short	ui_unit;	/* unit number on the system */
	short	ui_ctlr;	/* mass ctlr number; -1 if none */
	short	ui_ubanum;	/* the uba it is on */
	short	ui_slave;	/* slave on controller */
	int	(**ui_intr)();	/* interrupt handler(s) */
	caddr_t	ui_addr;	/* address of device in i/o space */
	short	ui_alive;	/* device exists */
	short	ui_type;	/* driver specific type information */
	short	ui_dk;		/* device number for iostat */
	caddr_t	ui_physaddr;	/* phys addr, for standalone (dump) code */
/* if the driver isn't also a controller, this is the controller it is on */
	struct	uba_minfo *ui_mi;
	struct	uba_hd *ui_hd;
};

#define	NUBA780	4
#define	NUBA750	1
#if VAX780
#define	MAXNUBA	4
#else
#define	MAXNUBA	1
#endif

/*
 * This structure exists per-uba.
 *
 * N.B.: THE SIZE AND SHAPE OF THIS STRUCTURE IS KNOWN IN uba.m.
 */
struct	uba_hd {
	int	uh_active;		/* bit per device transferring */
	struct	uba_regs *uh_uba;	/* virt addr of uba */
	struct	uba_regs *uh_physuba;	/* phys addr of uba */
	int	(**uh_vec)();		/* interrupt vector */
	struct	uba_minfo *uh_actf;	/* head of queue to transfer */
	struct	uba_minfo *uh_actl;	/* tail of queue to transfer */
	short	uh_mrwant;		/* someone is waiting for map reg */
	short	uh_bdpwant;		/* someone awaits bdp's */
	int	uh_bdpfree;		/* free bdp's */
	int	uh_hangcnt;		/* number of ticks hung */
	int	uh_zvcnt;		/* number of 0 vectors */
#define	UAMSIZ	50
	struct	map *uh_map;
} uba_hd[MAXNUBA];
#ifdef KERNEL
extern	struct	uba_minfo ubminit[];
extern	struct	uba_dinfo ubdinit[];
int	numuba;
#endif
/*
 * Each UNIBUS driver defines entries for a set of routines
 * as well as an array of types which are acceptable to it.
 */
struct uba_driver {
	int	(*ud_cntrlr)();		/* see if a driver is really there */
	int	(*ud_slave)();		/* see if a slave is there; init */
	int	(*ud_dgo)();		/* routine to stuff driver regs */
/* dgo is called back by the unibus (usu ubaalloc), when the bus is ready */
	short	ud_needexcl;		/* need exclusive use of uba (rk07) */
	u_short	*ud_addr;		/* device csr addresses */
	char	*ud_pname;
	struct	uba_dinfo **ud_dinfo;	/* backpointers to ubdinit structs */
	struct	uba_minfo **ud_minfo;	/* backpointers to ubminit structs */
};

/*
 * unibus maps
 */
#define	NBDP780	15
#define	NBDP750	3
#define	MAXNBDP	15

#define	NUBMREG	496

/*
 * flags to uba map/bdp allocation routines
 */
#define	UBA_NEEDBDP	1		/* transfer needs a bdp */
#define	UBA_CANTWAIT	2		/* don't block me */
#define	UBA_NEED16	3		/* need 16 bit addresses only */
Commit	Line	Data
ca89a8ee	1	/* ubavar.h 4.6 %G% */
1cb3d36a BJ	2
1cb3d36a BJ	3	/*
10a50234	4	* unibus adapter
1cb3d36a	5	*/
ca89a8ee BJ	6	#if VAX750
	7	#define UBA750 ((struct uba_regs *)0xf30000)
	8	#define UMEM750 ((u_short *)0xfc0000)
	9	#endif
1cb3d36a	10
10a50234	11	#if VAX780
1cb3d36a BJ	12	/*
	13	* UBA registers
	14	*/
1cb3d36a BJ	15	struct uba_regs
	16	{
	17	int uba_cnfgr;
	18	int uba_cr;
	19	int uba_sr;
	20	int uba_dcr;
	21	int uba_fmer;
	22	int uba_fubar;
	23	int pad1[2];
	24	int uba_brsvr[4];
	25	int uba_brrvr[4];
	26	int uba_dpr[16];
	27	int pad2[480];
	28	struct pte uba_map[496];
10a50234 BJ	29	int pad3[16];
	30	};
	31
	32	/* UBA control register, UBACR */
	33	#define UBA_MRD16 0x40000000 /* map reg disable bit 4 */
	34	#define UBA_MRD8 0x20000000 /* map reg disable bit 3 */
	35	#define UBA_MRD4 0x10000000 /* map reg disable bit 2 */
	36	#define UBA_MRD2 0x08000000 /* map reg disable bit 1 */
	37	#define UBA_MRD1 0x04000000 /* map reg disable bit 0 */
	38	#define UBA_IFS 0x00000040 /* interrupt field switch */
	39	#define UBA_BRIE 0x00000020 /* BR interrupt enable */
	40	#define UBA_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
	41	#define UBA_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
	42	#define UBA_CNFIE 0x00000004 /* configuration IE */
	43	#define UBA_UPF 0x00000002 /* UNIBUS power fail */
	44	#define UBA_ADINIT 0x00000001 /* adapter init */
	45
	46	/* UBA status register, UASR */
	47	#define UBA_BR7FULL 0x08000000 /* BR7 receive vector reg full */
	48	#define UBA_BR6FULL 0x04000000 /* BR6 receive vector reg full */
	49	#define UBA_BR5FULL 0x02000000 /* BR5 receive vector reg full */
	50	#define UBA_BR4FULL 0x01000000 /* BR4 receive vector reg full */
	51	#define UBA_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
	52	#define UBA_RDS 0x00000200 /* read data substitute */
	53	#define UBA_CRD 0x00000100 /* corrected read data */
	54	#define UBA_CXTER 0x00000080 /* command transmit error */
	55	#define UBA_CXTMO 0x00000040 /* command transmit timeout */
	56	#define UBA_DPPE 0x00000020 /* data path parity error */
	57	#define UBA_IVMR 0x00000010 /* invalid map register */
	58	#define UBA_MRPF 0x00000008 /* map register parity failure */
	59	#define UBA_LEB 0x00000004 /* lost error */
	60	#define UBA_UBSTO 0x00000002 /* UNIBUS select timeout */
	61	#define UBA_UBSSTO 0x00000001 /* UNIBUS slave sync timeout */
	62
	63	/* BR receive vector register, BRRVR */
	64	#define UBA_AIRI 0x80000000 /* adapter interrupt request */
	65	#define UBA_DIV 0x0000ffff /* device interrupt vector field */
	66	#endif
	67
	68	/* data path register, DPR */
	69	#if VAX780
	70	#define UBA_BNE 0x80000000 /* buffer not empty - purge */
	71	#define UBA_BTE 0x40000000 /* buffer transfer error */
	72	#define UBA_DPF 0x20000000 /* DP function (RO) */
	73	#define UBA_BS 0x007f0000 /* buffer state field */
	74	#define UBA_BUBA 0x0000ffff /* buffered UNIBUS address */
	75	#endif
	76	#if VAX750
	77	#define UBA_ERROR 0x20000000
	78	#define UBA_NXM 0x40000000
	79	#define UBA_UCE 0x20000000
	80	#define UBA_PURGE 0x00000001
	81	#endif
	82
	83	/* map register, MR */
	84	#define UBA_MRV 0x80000000 /* map register valid */
	85	#define UBA_BO 0x02000000 /* byte offset bit */
	86	#define UBA_DPDB 0x01e00000 /* data path designator field */
	87	#define UBA_SBIPFN 0x000fffff /* SBI page address field */
	88
	89	#define UBA_DPSHIFT 21 /* shift to data path designator */
	90
	91	/*
ca89a8ee BJ	92	* Each UNIBUS mass storage controller has uba_minfo structure,
ca89a8ee BJ	93	* and a uba_dinfo structure (as below) for each attached drive.
10a50234 BJ	94	*/
10a50234 BJ	95	struct uba_minfo {
ca89a8ee BJ	96	struct uba_driver *um_driver;
ca89a8ee BJ	97	short um_ctlr; /* controller index in driver */
10a50234 BJ	98	short um_ubanum; /* the uba it is on */
10a50234 BJ	99	short um_alive; /* controller exists */
ca89a8ee	100	int (*um_intr)(); / interrupt handler(s) */
10a50234	101	caddr_t um_addr; /* address of device in i/o space */
10a50234	102	struct uba_info *um_forw;
ca89a8ee BJ	103	struct uba_hd *um_hd;
ca89a8ee BJ	104	struct buf um_tab; /* queue for this controller */
1cb3d36a	105	};
10a50234	106	/*
ca89a8ee BJ	107	* Each UNIBUS device has a uba_dinfo structure.
	108	* If a controller has many drives attached, then there will
	109	* be several uba_dinfo structures associated with a single uba_minfo
10a50234 BJ	110	* structure.
	111	*/
	112	struct uba_dinfo {
	113	struct uba_driver *ui_driver;
10a50234	114	short ui_unit; /* unit number on the system */
ca89a8ee	115	short ui_ctlr; /* mass ctlr number; -1 if none */
10a50234 BJ	116	short ui_ubanum; /* the uba it is on */
	117	short ui_slave; /* slave on controller */
	118	int (*ui_intr)(); / interrupt handler(s) */
	119	caddr_t ui_addr; /* address of device in i/o space */
	120	short ui_alive; /* device exists */
	121	short ui_type; /* driver specific type information */
	122	short ui_dk; /* device number for iostat */
	123	caddr_t ui_physaddr; /* phys addr, for standalone (dump) code */
	124	/* if the driver isn't also a controller, this is the controller it is on */
	125	struct uba_minfo *ui_mi;
	126	struct uba_hd *ui_hd;
	127	};
	128
	129	#define NUBA780 4
	130	#define NUBA750 1
	131	#if VAX780
	132	#define MAXNUBA 4
	133	#else
	134	#define MAXNUBA 1
	135	#endif
466a1b4c	136
10a50234	137	/*
ca89a8ee BJ	138	* This structure exists per-uba.
	139	*
	140	* N.B.: THE SIZE AND SHAPE OF THIS STRUCTURE IS KNOWN IN uba.m.
10a50234 BJ	141	*/
	142	struct uba_hd {
	143	int uh_active; /* bit per device transferring */
	144	struct uba_regs uh_uba; / virt addr of uba */
	145	struct uba_regs uh_physuba; / phys addr of uba */
	146	int (*uh_vec)(); / interrupt vector */
	147	struct uba_minfo uh_actf; / head of queue to transfer */
	148	struct uba_minfo uh_actl; / tail of queue to transfer */
	149	short uh_mrwant; /* someone is waiting for map reg */
	150	short uh_bdpwant; /* someone awaits bdp's */
	151	int uh_bdpfree; /* free bdp's */
	152	int uh_hangcnt; /* number of ticks hung */
	153	int uh_zvcnt; /* number of 0 vectors */
ca89a8ee BJ	154	#define UAMSIZ 50
ca89a8ee BJ	155	struct map *uh_map;
10a50234 BJ	156	} uba_hd[MAXNUBA];
	157	#ifdef KERNEL
	158	extern struct uba_minfo ubminit[];
	159	extern struct uba_dinfo ubdinit[];
	160	int numuba;
	161	#endif
	162	/*
ca89a8ee	163	* Each UNIBUS driver defines entries for a set of routines
10a50234 BJ	164	* as well as an array of types which are acceptable to it.
	165	*/
	166	struct uba_driver {
	167	int (ud_cntrlr)(); / see if a driver is really there */
	168	int (ud_slave)(); / see if a slave is there; init */
	169	int (ud_dgo)(); / routine to stuff driver regs */
	170	/* dgo is called back by the unibus (usu ubaalloc), when the bus is ready */
10a50234 BJ	171	short ud_needexcl; /* need exclusive use of uba (rk07) */
	172	u_short ud_addr; / device csr addresses */
	173	char *ud_pname;
ca89a8ee BJ	174	struct uba_dinfo *ud_dinfo; / backpointers to ubdinit structs */
ca89a8ee BJ	175	struct uba_minfo *ud_minfo; / backpointers to ubminit structs */
466a1b4c BJ	176	};
466a1b4c BJ	177
10a50234 BJ	178	/*
	179	* unibus maps
	180	*/
	181	#define NBDP780 15
	182	#define NBDP750 3
	183	#define MAXNBDP 15
	184
	185	#define NUBMREG 496
	186
	187	/*
	188	* flags to uba map/bdp allocation routines
	189	*/
	190	#define UBA_NEEDBDP 1 /* transfer needs a bdp */
	191	#define UBA_CANTWAIT 2 /* don't block me */
	192	#define UBA_NEED16 3 /* need 16 bit addresses only */