Commit | Line | Data |
---|---|---|
43d66181 | 1 | /* ht.c 4.23 82/07/13 */ |
0deaf016 | 2 | |
89bd2f01 | 3 | #include "tu.h" |
a5cc519e | 4 | #if NHT > 0 |
786dff00 | 5 | /* |
fcc37d29 | 6 | * TM03/TU?? tape driver |
d565635a BJ |
7 | * |
8 | * TODO: | |
3ee331b1 | 9 | * cleanup messages on errors |
d565635a BJ |
10 | * test ioctl's |
11 | * see how many rewind interrups we get if we kick when not at BOT | |
3ee331b1 | 12 | * fixup rle error on block tape code |
786dff00 | 13 | */ |
786dff00 BJ |
14 | #include "../h/param.h" |
15 | #include "../h/systm.h" | |
16 | #include "../h/buf.h" | |
17 | #include "../h/conf.h" | |
18 | #include "../h/dir.h" | |
19 | #include "../h/file.h" | |
20 | #include "../h/user.h" | |
21 | #include "../h/map.h" | |
80e7c811 | 22 | #include "../h/pte.h" |
89bd2f01 BJ |
23 | #include "../h/mbareg.h" |
24 | #include "../h/mbavar.h" | |
fcc37d29 BJ |
25 | #include "../h/mtio.h" |
26 | #include "../h/ioctl.h" | |
f0a3ddbd | 27 | #include "../h/cmap.h" |
0deaf016 | 28 | #include "../h/cpu.h" |
786dff00 | 29 | |
fcc37d29 BJ |
30 | #include "../h/htreg.h" |
31 | ||
32 | struct buf rhtbuf[NHT]; | |
33 | struct buf chtbuf[NHT]; | |
34 | ||
35 | short httypes[] = | |
fc4d0a69 | 36 | { MBDT_TM03, MBDT_TE16, MBDT_TU45, MBDT_TU77, 0 }; |
89bd2f01 | 37 | struct mba_device *htinfo[NHT]; |
a0eab615 | 38 | int htattach(), htslave(), htustart(), htndtint(), htdtint(); |
fcc37d29 | 39 | struct mba_driver htdriver = |
89bd2f01 BJ |
40 | { htattach, htslave, htustart, 0, htdtint, htndtint, |
41 | httypes, "ht", "tu", htinfo }; | |
fcc37d29 BJ |
42 | |
43 | #define MASKREG(r) ((r) & 0xffff) | |
44 | ||
45 | /* bits in minor device */ | |
89bd2f01 | 46 | #define TUUNIT(dev) (minor(dev)&03) |
fcc37d29 BJ |
47 | #define H_NOREWIND 04 |
48 | #define H_1600BPI 08 | |
786dff00 | 49 | |
d565635a | 50 | #define HTUNIT(dev) (tutoht[TUUNIT(dev)]) |
89bd2f01 | 51 | |
fcc37d29 BJ |
52 | #define INF (daddr_t)1000000L /* a block number that wont exist */ |
53 | ||
d565635a | 54 | struct tu_softc { |
fcc37d29 BJ |
55 | char sc_openf; |
56 | char sc_flags; | |
57 | daddr_t sc_blkno; | |
58 | daddr_t sc_nxrec; | |
59 | u_short sc_erreg; | |
60 | u_short sc_dsreg; | |
61 | short sc_resid; | |
62 | short sc_dens; | |
89bd2f01 BJ |
63 | struct mba_device *sc_mi; |
64 | int sc_slave; | |
d565635a BJ |
65 | } tu_softc[NTU]; |
66 | short tutoht[NTU]; | |
fcc37d29 | 67 | |
fcc37d29 BJ |
68 | /* |
69 | * Bits for sc_flags. | |
70 | */ | |
71 | #define H_WRITTEN 1 /* last operation was a write */ | |
72 | #define H_ERASED 2 /* last write retry was an erase gap */ | |
73 | #define H_REWIND 4 /* last unit start was a rewind */ | |
786dff00 | 74 | |
3ee331b1 BJ |
75 | char hter_bits[] = HTER_BITS; |
76 | char htds_bits[] = HTDS_BITS; | |
77 | ||
fcc37d29 | 78 | /*ARGSUSED*/ |
89bd2f01 BJ |
79 | htattach(mi) |
80 | struct mba_device *mi; | |
81 | { | |
82 | ||
83 | } | |
84 | ||
85 | htslave(mi, ms) | |
86 | struct mba_device *mi; | |
87 | struct mba_slave *ms; | |
fcc37d29 | 88 | { |
d565635a | 89 | register struct tu_softc *sc = &tu_softc[ms->ms_unit]; |
64614526 BJ |
90 | register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; |
91 | ||
92 | htaddr->httc = ms->ms_slave; | |
93 | if (htaddr->htdt & HTDT_SPR) { | |
94 | sc->sc_mi = mi; | |
95 | sc->sc_slave = ms->ms_slave; | |
96 | tutoht[ms->ms_unit] = mi->mi_unit; | |
97 | return (1); | |
98 | } else | |
99 | return (0); | |
fcc37d29 | 100 | } |
786dff00 BJ |
101 | |
102 | htopen(dev, flag) | |
fcc37d29 BJ |
103 | dev_t dev; |
104 | int flag; | |
786dff00 | 105 | { |
d565635a | 106 | register int tuunit; |
89bd2f01 | 107 | register struct mba_device *mi; |
d565635a | 108 | register struct tu_softc *sc; |
cd470e1d | 109 | int olddens, dens; |
786dff00 | 110 | |
d565635a BJ |
111 | tuunit = TUUNIT(dev); |
112 | if (tuunit >= NTU || (sc = &tu_softc[tuunit])->sc_openf || | |
89bd2f01 | 113 | (mi = htinfo[HTUNIT(dev)]) == 0 || mi->mi_alive == 0) { |
786dff00 BJ |
114 | u.u_error = ENXIO; |
115 | return; | |
116 | } | |
cd470e1d | 117 | olddens = sc->sc_dens; |
3ee331b1 | 118 | dens = sc->sc_dens = |
d565635a BJ |
119 | ((minor(dev)&H_1600BPI)?HTTC_1600BPI:HTTC_800BPI)| |
120 | HTTC_PDP11|sc->sc_slave; | |
cd470e1d BJ |
121 | htcommand(dev, HT_SENSE, 1); |
122 | sc->sc_dens = olddens; | |
61add2a3 | 123 | if ((sc->sc_dsreg & HTDS_MOL) == 0) { |
1d78646d | 124 | uprintf("tu%d: not online\n", tuunit); |
61add2a3 BJ |
125 | u.u_error = EIO; |
126 | return; | |
127 | } | |
128 | if ((flag&FWRITE) && (sc->sc_dsreg&HTDS_WRL)) { | |
1d78646d | 129 | uprintf("tu%d: no write ring\n", tuunit); |
61add2a3 BJ |
130 | u.u_error = EIO; |
131 | return; | |
132 | } | |
133 | if ((sc->sc_dsreg & HTDS_BOT) == 0 && (flag&FWRITE) && | |
134 | dens != sc->sc_dens) { | |
1d78646d | 135 | uprintf("tu%d: can't change density in mid-tape\n", tuunit); |
fcc37d29 BJ |
136 | u.u_error = EIO; |
137 | return; | |
138 | } | |
fcc37d29 BJ |
139 | sc->sc_openf = 1; |
140 | sc->sc_blkno = (daddr_t)0; | |
141 | sc->sc_nxrec = INF; | |
142 | sc->sc_flags = 0; | |
d565635a | 143 | sc->sc_dens = dens; |
786dff00 BJ |
144 | } |
145 | ||
146 | htclose(dev, flag) | |
fcc37d29 BJ |
147 | register dev_t dev; |
148 | register flag; | |
786dff00 | 149 | { |
d565635a | 150 | register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; |
786dff00 | 151 | |
fcc37d29 BJ |
152 | if (flag == FWRITE || ((flag&FWRITE) && (sc->sc_flags&H_WRITTEN))) { |
153 | htcommand(dev, HT_WEOF, 1); | |
154 | htcommand(dev, HT_WEOF, 1); | |
155 | htcommand(dev, HT_SREV, 1); | |
786dff00 | 156 | } |
fcc37d29 | 157 | if ((minor(dev)&H_NOREWIND) == 0) |
fcc37d29 BJ |
158 | htcommand(dev, HT_REW, 0); |
159 | sc->sc_openf = 0; | |
786dff00 BJ |
160 | } |
161 | ||
fcc37d29 BJ |
162 | htcommand(dev, com, count) |
163 | dev_t dev; | |
164 | int com, count; | |
786dff00 BJ |
165 | { |
166 | register struct buf *bp; | |
2311123d | 167 | register int s; |
786dff00 | 168 | |
fcc37d29 | 169 | bp = &chtbuf[HTUNIT(dev)]; |
2311123d | 170 | s = spl5(); |
fcc37d29 | 171 | while (bp->b_flags&B_BUSY) { |
9f1dae18 | 172 | if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) |
89bd2f01 | 173 | break; |
786dff00 BJ |
174 | bp->b_flags |= B_WANTED; |
175 | sleep((caddr_t)bp, PRIBIO); | |
176 | } | |
dc637456 | 177 | bp->b_flags = B_BUSY|B_READ; |
2311123d | 178 | splx(s); |
786dff00 | 179 | bp->b_dev = dev; |
fcc37d29 BJ |
180 | bp->b_command = com; |
181 | bp->b_repcnt = count; | |
786dff00 | 182 | bp->b_blkno = 0; |
786dff00 | 183 | htstrategy(bp); |
fcc37d29 BJ |
184 | if (count == 0) |
185 | return; | |
786dff00 | 186 | iowait(bp); |
fcc37d29 | 187 | if (bp->b_flags&B_WANTED) |
786dff00 | 188 | wakeup((caddr_t)bp); |
fcc37d29 | 189 | bp->b_flags &= B_ERROR; |
786dff00 BJ |
190 | } |
191 | ||
192 | htstrategy(bp) | |
fcc37d29 | 193 | register struct buf *bp; |
786dff00 | 194 | { |
d565635a | 195 | register struct mba_device *mi = htinfo[HTUNIT(bp->b_dev)]; |
fcc37d29 | 196 | register struct buf *dp; |
2311123d | 197 | register int s; |
786dff00 | 198 | |
786dff00 | 199 | bp->av_forw = NULL; |
fcc37d29 | 200 | dp = &mi->mi_tab; |
2311123d | 201 | s = spl5(); |
fcc37d29 BJ |
202 | if (dp->b_actf == NULL) |
203 | dp->b_actf = bp; | |
786dff00 | 204 | else |
fcc37d29 BJ |
205 | dp->b_actl->av_forw = bp; |
206 | dp->b_actl = bp; | |
207 | if (dp->b_active == 0) | |
208 | mbustart(mi); | |
2311123d | 209 | splx(s); |
786dff00 BJ |
210 | } |
211 | ||
fcc37d29 | 212 | htustart(mi) |
89bd2f01 | 213 | register struct mba_device *mi; |
786dff00 | 214 | { |
fcc37d29 BJ |
215 | register struct htdevice *htaddr = |
216 | (struct htdevice *)mi->mi_drv; | |
217 | register struct buf *bp = mi->mi_tab.b_actf; | |
d565635a | 218 | register struct tu_softc *sc = &tu_softc[TUUNIT(bp->b_dev)]; |
786dff00 BJ |
219 | daddr_t blkno; |
220 | ||
fcc37d29 | 221 | htaddr->httc = sc->sc_dens; |
fc4d0a69 | 222 | if (bp == &chtbuf[HTUNIT(bp->b_dev)] && bp->b_command == HT_SENSE) { |
9f1dae18 BJ |
223 | htaddr->htcs1 = HT_SENSE|HT_GO; |
224 | mbclrattn(mi); | |
225 | } | |
fcc37d29 BJ |
226 | sc->sc_dsreg = htaddr->htds; |
227 | sc->sc_erreg = htaddr->hter; | |
228 | sc->sc_resid = htaddr->htfc; | |
229 | sc->sc_flags &= ~(H_WRITTEN|H_REWIND); | |
230 | if ((htaddr->htdt & HTDT_SPR) == 0 || (htaddr->htds & HTDS_MOL) == 0) | |
231 | if (sc->sc_openf > 0) | |
232 | sc->sc_openf = -1; | |
233 | if (sc->sc_openf < 0) { | |
234 | bp->b_flags |= B_ERROR; | |
235 | return (MBU_NEXT); | |
236 | } | |
d565635a | 237 | if (bp != &chtbuf[HTUNIT(bp->b_dev)]) { |
43d66181 | 238 | if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { |
fcc37d29 BJ |
239 | bp->b_flags |= B_ERROR; |
240 | bp->b_error = ENXIO; | |
0deaf016 | 241 | return (MBU_NEXT); |
d565635a | 242 | } |
43d66181 | 243 | if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && |
fcc37d29 BJ |
244 | bp->b_flags&B_READ) { |
245 | bp->b_resid = bp->b_bcount; | |
246 | clrbuf(bp); | |
0deaf016 | 247 | return (MBU_NEXT); |
d565635a BJ |
248 | } |
249 | if ((bp->b_flags&B_READ)==0) | |
43d66181 | 250 | sc->sc_nxrec = bdbtofsb(bp->b_blkno) + 1; |
fcc37d29 | 251 | } else { |
0deaf016 | 252 | if (bp->b_command == HT_SENSE) |
fcc37d29 BJ |
253 | return (MBU_NEXT); |
254 | if (bp->b_command == HT_REW) | |
255 | sc->sc_flags |= H_REWIND; | |
256 | else | |
257 | htaddr->htfc = -bp->b_bcount; | |
258 | htaddr->htcs1 = bp->b_command|HT_GO; | |
259 | return (MBU_STARTED); | |
260 | } | |
43d66181 | 261 | if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { |
fcc37d29 BJ |
262 | htaddr->htfc = -bp->b_bcount; |
263 | if ((bp->b_flags&B_READ) == 0) { | |
d565635a BJ |
264 | if (mi->mi_tab.b_errcnt) { |
265 | if ((sc->sc_flags & H_ERASED) == 0) { | |
fcc37d29 BJ |
266 | sc->sc_flags |= H_ERASED; |
267 | htaddr->htcs1 = HT_ERASE | HT_GO; | |
268 | return (MBU_STARTED); | |
269 | } | |
d565635a BJ |
270 | sc->sc_flags &= ~H_ERASED; |
271 | } | |
fcc37d29 BJ |
272 | if (htaddr->htds & HTDS_EOT) { |
273 | bp->b_resid = bp->b_bcount; | |
b0130242 | 274 | bp->b_flags |= B_ERROR; |
fcc37d29 BJ |
275 | return (MBU_NEXT); |
276 | } | |
786dff00 | 277 | } |
fcc37d29 | 278 | return (MBU_DODATA); |
786dff00 | 279 | } |
43d66181 SL |
280 | if (blkno < bdbtofsb(bp->b_blkno)) { |
281 | htaddr->htfc = blkno - bdbtofsb(bp->b_blkno); | |
fcc37d29 | 282 | htaddr->htcs1 = HT_SFORW|HT_GO; |
786dff00 | 283 | } else { |
43d66181 | 284 | htaddr->htfc = bdbtofsb(bp->b_blkno) - blkno; |
fcc37d29 | 285 | htaddr->htcs1 = HT_SREV|HT_GO; |
786dff00 | 286 | } |
fcc37d29 | 287 | return (MBU_STARTED); |
786dff00 BJ |
288 | } |
289 | ||
d565635a | 290 | htdtint(mi, mbsr) |
89bd2f01 | 291 | register struct mba_device *mi; |
d565635a | 292 | int mbsr; |
786dff00 | 293 | { |
fcc37d29 BJ |
294 | register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; |
295 | register struct buf *bp = mi->mi_tab.b_actf; | |
d565635a | 296 | register struct tu_softc *sc; |
0deaf016 | 297 | int ds, er, mbs; |
786dff00 | 298 | |
d565635a | 299 | sc = &tu_softc[TUUNIT(bp->b_dev)]; |
fcc37d29 BJ |
300 | ds = sc->sc_dsreg = MASKREG(htaddr->htds); |
301 | er = sc->sc_erreg = MASKREG(htaddr->hter); | |
302 | sc->sc_resid = MASKREG(htaddr->htfc); | |
d565635a | 303 | mbs = mbsr; |
fcc37d29 BJ |
304 | sc->sc_blkno++; |
305 | if((bp->b_flags & B_READ) == 0) | |
306 | sc->sc_flags |= H_WRITTEN; | |
d565635a | 307 | if ((ds&(HTDS_ERR|HTDS_MOL)) != HTDS_MOL || mbs & MBSR_EBITS) { |
fcc37d29 | 308 | htaddr->htcs1 = HT_DCLR|HT_GO; |
0deaf016 BJ |
309 | mbclrattn(mi); |
310 | if (bp == &rhtbuf[HTUNIT(bp->b_dev)]) { | |
fcc37d29 | 311 | er &= ~HTER_FCE; |
d565635a | 312 | mbs &= ~(MBSR_DTABT|MBSR_MBEXC); |
ea59de47 | 313 | } |
fcc37d29 BJ |
314 | if (bp->b_flags & B_READ && ds & HTDS_PES) |
315 | er &= ~(HTER_CSITM|HTER_CORCRC); | |
d565635a | 316 | if (er&HTER_HARD || mbs&MBSR_EBITS || (ds&HTDS_MOL) == 0 || |
0deaf016 | 317 | er && ++mi->mi_tab.b_errcnt >= 7) { |
fcc37d29 BJ |
318 | if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) |
319 | sc->sc_openf = -1; | |
9f1dae18 BJ |
320 | if ((er&HTER_HARD) == HTER_FCE && |
321 | (mbs&MBSR_EBITS) == (MBSR_DTABT|MBSR_MBEXC) && | |
322 | (ds&HTDS_MOL)) | |
323 | goto noprint; | |
3ee331b1 | 324 | printf("tu%d: hard error bn%d mbsr=%b er=%b ds=%b\n", |
89bd2f01 | 325 | TUUNIT(bp->b_dev), bp->b_blkno, |
d565635a | 326 | mbsr, mbsr_bits, |
3ee331b1 BJ |
327 | sc->sc_erreg, hter_bits, |
328 | sc->sc_dsreg, htds_bits); | |
9f1dae18 | 329 | noprint: |
786dff00 | 330 | bp->b_flags |= B_ERROR; |
fcc37d29 | 331 | return (MBD_DONE); |
786dff00 | 332 | } |
fcc37d29 BJ |
333 | if (er) |
334 | return (MBD_RETRY); | |
786dff00 | 335 | } |
fcc37d29 BJ |
336 | bp->b_resid = 0; |
337 | if (bp->b_flags & B_READ) | |
338 | if (ds&HTDS_TM) { /* must be a read, right? */ | |
339 | bp->b_resid = bp->b_bcount; | |
43d66181 | 340 | sc->sc_nxrec = bdbtofsb(bp->b_blkno); |
fcc37d29 BJ |
341 | } else if(bp->b_bcount > MASKREG(htaddr->htfc)) |
342 | bp->b_resid = bp->b_bcount - MASKREG(htaddr->htfc); | |
343 | return (MBD_DONE); | |
344 | } | |
786dff00 | 345 | |
fcc37d29 | 346 | htndtint(mi) |
89bd2f01 | 347 | register struct mba_device *mi; |
fcc37d29 BJ |
348 | { |
349 | register struct htdevice *htaddr = (struct htdevice *)mi->mi_drv; | |
350 | register struct buf *bp = mi->mi_tab.b_actf; | |
d565635a | 351 | register struct tu_softc *sc; |
fcc37d29 | 352 | int er, ds, fc; |
786dff00 | 353 | |
d565635a BJ |
354 | ds = MASKREG(htaddr->htds); |
355 | er = MASKREG(htaddr->hter); | |
356 | fc = MASKREG(htaddr->htfc); | |
357 | if (er) { | |
fcc37d29 | 358 | htaddr->htcs1 = HT_DCLR|HT_GO; |
0deaf016 BJ |
359 | mbclrattn(mi); |
360 | } | |
d565635a BJ |
361 | if (bp == 0) |
362 | return (MBN_SKIP); | |
363 | sc = &tu_softc[TUUNIT(bp->b_dev)]; | |
364 | sc->sc_dsreg = ds; | |
365 | sc->sc_erreg = er; | |
366 | sc->sc_resid = fc; | |
367 | if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { | |
368 | switch (bp->b_command) { | |
369 | case HT_REWOFFL: | |
fcc37d29 BJ |
370 | /* offline is on purpose; don't do anything special */ |
371 | ds |= HTDS_MOL; | |
d565635a BJ |
372 | break; |
373 | case HT_SREV: | |
374 | /* if backspace file hit bot, its not an error */ | |
375 | if (er == (HTER_NEF|HTER_FCE) && ds&HTDS_BOT && | |
376 | bp->b_repcnt == INF) | |
377 | er &= ~HTER_NEF; | |
378 | break; | |
379 | } | |
fcc37d29 BJ |
380 | er &= ~HTER_FCE; |
381 | if (er == 0) | |
382 | ds &= ~HTDS_ERR; | |
383 | } | |
384 | if ((ds & (HTDS_ERR|HTDS_MOL)) != HTDS_MOL) { | |
385 | if ((ds & HTDS_MOL) == 0 && sc->sc_openf > 0) | |
386 | sc->sc_openf = -1; | |
3ee331b1 | 387 | printf("tu%d: hard error bn%d er=%b ds=%b\n", |
89bd2f01 | 388 | TUUNIT(bp->b_dev), bp->b_blkno, |
3ee331b1 | 389 | sc->sc_erreg, hter_bits, sc->sc_dsreg, htds_bits); |
fcc37d29 BJ |
390 | bp->b_flags |= B_ERROR; |
391 | return (MBN_DONE); | |
786dff00 | 392 | } |
d565635a | 393 | if (bp == &chtbuf[HTUNIT(bp->b_dev)]) { |
fcc37d29 BJ |
394 | if (sc->sc_flags & H_REWIND) |
395 | return (ds & HTDS_BOT ? MBN_DONE : MBN_RETRY); | |
396 | bp->b_resid = -sc->sc_resid; | |
397 | return (MBN_DONE); | |
398 | } | |
399 | if (ds & HTDS_TM) | |
43d66181 SL |
400 | if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { |
401 | sc->sc_nxrec = bdbtofsb(bp->b_blkno) - fc; | |
fcc37d29 | 402 | sc->sc_blkno = sc->sc_nxrec; |
d565635a | 403 | } else { |
43d66181 | 404 | sc->sc_blkno = bdbtofsb(bp->b_blkno) + fc; |
fcc37d29 BJ |
405 | sc->sc_nxrec = sc->sc_blkno - 1; |
406 | } | |
407 | else | |
43d66181 | 408 | sc->sc_blkno = bdbtofsb(bp->b_blkno); |
fcc37d29 | 409 | return (MBN_RETRY); |
786dff00 BJ |
410 | } |
411 | ||
412 | htread(dev) | |
fcc37d29 | 413 | dev_t dev; |
786dff00 | 414 | { |
fcc37d29 | 415 | |
786dff00 | 416 | htphys(dev); |
fcc37d29 BJ |
417 | if (u.u_error) |
418 | return; | |
419 | physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_READ, minphys); | |
786dff00 BJ |
420 | } |
421 | ||
422 | htwrite(dev) | |
423 | { | |
fcc37d29 | 424 | |
786dff00 | 425 | htphys(dev); |
fcc37d29 BJ |
426 | if (u.u_error) |
427 | return; | |
428 | physio(htstrategy, &rhtbuf[HTUNIT(dev)], dev, B_WRITE, minphys); | |
786dff00 BJ |
429 | } |
430 | ||
431 | htphys(dev) | |
fcc37d29 | 432 | dev_t dev; |
786dff00 | 433 | { |
d565635a BJ |
434 | register int htunit; |
435 | register struct tu_softc *sc; | |
436 | register struct mba_device *mi; | |
786dff00 BJ |
437 | daddr_t a; |
438 | ||
d565635a BJ |
439 | htunit = HTUNIT(dev); |
440 | if (htunit >= NHT || (mi = htinfo[htunit]) == 0 || mi->mi_alive == 0) { | |
fcc37d29 BJ |
441 | u.u_error = ENXIO; |
442 | return; | |
786dff00 | 443 | } |
fcc37d29 | 444 | a = u.u_offset >> 9; |
d565635a | 445 | sc = &tu_softc[TUUNIT(dev)]; |
43d66181 SL |
446 | sc->sc_blkno = bdbtofsb(a); |
447 | sc->sc_nxrec = bdbtofsb(a)+1; | |
786dff00 | 448 | } |
f0a3ddbd | 449 | |
fcc37d29 BJ |
450 | /*ARGSUSED*/ |
451 | htioctl(dev, cmd, addr, flag) | |
452 | dev_t dev; | |
453 | int cmd; | |
454 | caddr_t addr; | |
455 | int flag; | |
456 | { | |
d565635a BJ |
457 | register struct tu_softc *sc = &tu_softc[TUUNIT(dev)]; |
458 | register struct buf *bp = &chtbuf[HTUNIT(dev)]; | |
fcc37d29 BJ |
459 | register callcount; |
460 | int fcount; | |
461 | struct mtop mtop; | |
462 | struct mtget mtget; | |
463 | /* we depend of the values and order of the MT codes here */ | |
464 | static htops[] = | |
465 | {HT_WEOF,HT_SFORW,HT_SREV,HT_SFORW,HT_SREV,HT_REW,HT_REWOFFL,HT_SENSE}; | |
466 | ||
467 | switch (cmd) { | |
468 | case MTIOCTOP: /* tape operation */ | |
469 | if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { | |
470 | u.u_error = EFAULT; | |
471 | return; | |
472 | } | |
473 | switch(mtop.mt_op) { | |
474 | case MTWEOF: | |
475 | callcount = mtop.mt_count; | |
476 | fcount = 1; | |
477 | break; | |
478 | case MTFSF: case MTBSF: | |
479 | callcount = mtop.mt_count; | |
480 | fcount = INF; | |
481 | break; | |
482 | case MTFSR: case MTBSR: | |
483 | callcount = 1; | |
484 | fcount = mtop.mt_count; | |
485 | break; | |
486 | case MTREW: case MTOFFL: | |
487 | callcount = 1; | |
488 | fcount = 1; | |
489 | break; | |
490 | default: | |
491 | u.u_error = ENXIO; | |
492 | return; | |
493 | } | |
494 | if (callcount <= 0 || fcount <= 0) { | |
495 | u.u_error = ENXIO; | |
496 | return; | |
497 | } | |
498 | while (--callcount >= 0) { | |
499 | htcommand(dev, htops[mtop.mt_op], fcount); | |
500 | if ((mtop.mt_op == MTFSR || mtop.mt_op == MTBSR) && | |
501 | bp->b_resid) { | |
502 | u.u_error = EIO; | |
503 | break; | |
504 | } | |
d565635a | 505 | if ((bp->b_flags&B_ERROR) || sc->sc_dsreg&HTDS_BOT) |
fcc37d29 BJ |
506 | break; |
507 | } | |
508 | geterror(bp); | |
509 | return; | |
510 | case MTIOCGET: | |
511 | mtget.mt_dsreg = sc->sc_dsreg; | |
512 | mtget.mt_erreg = sc->sc_erreg; | |
513 | mtget.mt_resid = sc->sc_resid; | |
e320a1c9 | 514 | mtget.mt_type = MT_ISHT; |
fcc37d29 BJ |
515 | if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) |
516 | u.u_error = EFAULT; | |
517 | return; | |
518 | default: | |
519 | u.u_error = ENXIO; | |
520 | } | |
521 | } | |
f0a3ddbd BJ |
522 | |
523 | #define DBSIZE 20 | |
524 | ||
fcc37d29 | 525 | htdump() |
f0a3ddbd | 526 | { |
89bd2f01 | 527 | register struct mba_device *mi; |
fcc37d29 BJ |
528 | register struct mba_regs *mp; |
529 | register struct htdevice *htaddr; | |
530 | int blk, num; | |
531 | int start; | |
532 | ||
533 | start = 0; | |
534 | num = maxfree; | |
535 | #define phys(a,b) ((b)((int)(a)&0x7fffffff)) | |
536 | if (htinfo[0] == 0) | |
537 | return (ENXIO); | |
89bd2f01 | 538 | mi = phys(htinfo[0], struct mba_device *); |
fcc37d29 | 539 | mp = phys(mi->mi_hd, struct mba_hd *)->mh_physmba; |
9f1dae18 | 540 | mp->mba_cr = MBCR_IE; |
fcc37d29 BJ |
541 | htaddr = (struct htdevice *)&mp->mba_drv[mi->mi_drive]; |
542 | htaddr->httc = HTTC_PDP11|HTTC_1600BPI; | |
543 | htaddr->htcs1 = HT_DCLR|HT_GO; | |
f0a3ddbd BJ |
544 | while (num > 0) { |
545 | blk = num > DBSIZE ? DBSIZE : num; | |
fcc37d29 BJ |
546 | htdwrite(start, blk, htaddr, mp); |
547 | start += blk; | |
f0a3ddbd BJ |
548 | num -= blk; |
549 | } | |
fcc37d29 BJ |
550 | hteof(htaddr); |
551 | hteof(htaddr); | |
9f1dae18 | 552 | htwait(htaddr); |
fc4d0a69 | 553 | if (htaddr->htds&HTDS_ERR) |
9f1dae18 BJ |
554 | return (EIO); |
555 | htaddr->htcs1 = HT_REW|HT_GO; | |
a0eab615 | 556 | return (0); |
f0a3ddbd BJ |
557 | } |
558 | ||
fcc37d29 BJ |
559 | htdwrite(dbuf, num, htaddr, mp) |
560 | register dbuf, num; | |
561 | register struct htdevice *htaddr; | |
562 | struct mba_regs *mp; | |
f0a3ddbd | 563 | { |
fcc37d29 | 564 | register struct pte *io; |
f0a3ddbd BJ |
565 | register int i; |
566 | ||
fcc37d29 BJ |
567 | htwait(htaddr); |
568 | io = mp->mba_map; | |
f0a3ddbd | 569 | for (i = 0; i < num; i++) |
fcc37d29 BJ |
570 | *(int *)io++ = dbuf++ | PG_V; |
571 | htaddr->htfc = -(num*NBPG); | |
572 | mp->mba_sr = -1; | |
573 | mp->mba_bcr = -(num*NBPG); | |
574 | mp->mba_var = 0; | |
575 | htaddr->htcs1 = HT_WCOM|HT_GO; | |
f0a3ddbd BJ |
576 | } |
577 | ||
fcc37d29 BJ |
578 | htwait(htaddr) |
579 | struct htdevice *htaddr; | |
f0a3ddbd BJ |
580 | { |
581 | register s; | |
582 | ||
583 | do | |
fcc37d29 BJ |
584 | s = htaddr->htds; |
585 | while ((s & HTDS_DRY) == 0); | |
f0a3ddbd BJ |
586 | } |
587 | ||
fcc37d29 BJ |
588 | hteof(htaddr) |
589 | struct htdevice *htaddr; | |
f0a3ddbd BJ |
590 | { |
591 | ||
fcc37d29 BJ |
592 | htwait(htaddr); |
593 | htaddr->htcs1 = HT_WEOF|HT_GO; | |
f0a3ddbd | 594 | } |
a5cc519e | 595 | #endif |