Commit | Line | Data |
---|---|---|
cd1b1cd4 | 1 | /* dh.c 4.30 81/03/09 */ |
a18f326f | 2 | |
66b4fb09 | 3 | #include "dh.h" |
0916e0d1 | 4 | #if NDH > 0 |
a18f326f | 5 | /* |
d4638843 | 6 | * DH-11/DM-11 driver |
a18f326f | 7 | */ |
e2c4935e | 8 | #include "bk.h" |
a18f326f BJ |
9 | #include "../h/param.h" |
10 | #include "../h/conf.h" | |
11 | #include "../h/dir.h" | |
12 | #include "../h/user.h" | |
13 | #include "../h/tty.h" | |
14 | #include "../h/map.h" | |
15 | #include "../h/pte.h" | |
3f3a34c3 | 16 | #include "../h/buf.h" |
7e286c72 | 17 | #include "../h/vm.h" |
b09915c5 BJ |
18 | #include "../h/ubareg.h" |
19 | #include "../h/ubavar.h" | |
038bbe6b | 20 | #include "../h/bk.h" |
a5cc519e | 21 | #include "../h/clist.h" |
1b05b375 | 22 | #include "../h/mx.h" |
7e00c42b | 23 | #include "../h/file.h" |
a18f326f | 24 | |
7e00c42b | 25 | /* |
d4638843 BJ |
26 | * Definition of the driver for the auto-configuration program. |
27 | * There is one definition for the dh and one for the dm. | |
7e00c42b | 28 | */ |
71236e46 | 29 | int dhprobe(), dhattach(), dhrint(), dhxint(); |
b09915c5 | 30 | struct uba_device *dhinfo[NDH]; |
3f3a34c3 | 31 | u_short dhstd[] = { 0 }; |
3f3a34c3 | 32 | struct uba_driver dhdriver = |
71236e46 | 33 | { dhprobe, 0, dhattach, 0, dhstd, "dh", dhinfo }; |
3f3a34c3 | 34 | |
71236e46 | 35 | int dmprobe(), dmattach(), dmintr(); |
b09915c5 | 36 | struct uba_device *dminfo[NDH]; |
d4638843 BJ |
37 | u_short dmstd[] = { 0 }; |
38 | struct uba_driver dmdriver = | |
71236e46 | 39 | { dmprobe, 0, dmattach, 0, dmstd, "dm", dminfo }; |
a18f326f | 40 | |
d4638843 BJ |
41 | struct dhdevice |
42 | { | |
43 | union { | |
44 | short dhcsr; /* control-status register */ | |
45 | char dhcsrl; /* low byte for line select */ | |
46 | } un; | |
47 | short dhrcr; /* receive character register */ | |
48 | short dhlpr; /* line parameter register */ | |
49 | u_short dhcar; /* current address register */ | |
50 | short dhbcr; /* byte count register */ | |
51 | u_short dhbar; /* buffer active register */ | |
52 | short dhbreak; /* break control register */ | |
53 | short dhsilo; /* silo status register */ | |
54 | }; | |
a18f326f | 55 | |
88d5b764 BJ |
56 | /* Bits in dhcsr */ |
57 | #define DH_TI 0100000 /* transmit interrupt */ | |
58 | #define DH_SI 0040000 /* storage interrupt */ | |
59 | #define DH_TIE 0020000 /* transmit interrupt enable */ | |
60 | #define DH_SIE 0010000 /* storage interrupt enable */ | |
61 | #define DH_MC 0004000 /* master clear */ | |
62 | #define DH_NXM 0002000 /* non-existant memory */ | |
63 | #define DH_MM 0001000 /* maintenance mode */ | |
64 | #define DH_CNI 0000400 /* clear non-existant memory interrupt */ | |
65 | #define DH_RI 0000200 /* receiver interrupt */ | |
66 | #define DH_RIE 0000100 /* receiver interrupt enable */ | |
67 | ||
d4638843 BJ |
68 | /* Bits in dhlpr */ |
69 | #define BITS6 01 | |
70 | #define BITS7 02 | |
71 | #define BITS8 03 | |
72 | #define TWOSB 04 | |
73 | #define PENABLE 020 | |
74 | /* DEC manuals incorrectly say this bit causes generation of even parity. */ | |
75 | #define OPAR 040 | |
76 | #define HDUPLX 040000 | |
77 | ||
88d5b764 BJ |
78 | #define DH_IE (DH_TIE|DH_SIE|DH_RIE) |
79 | ||
80 | /* Bits in dhrcr */ | |
d4638843 BJ |
81 | #define DH_PE 0010000 /* parity error */ |
82 | #define DH_FE 0020000 /* framing error */ | |
83 | #define DH_DO 0040000 /* data overrun */ | |
84 | ||
85 | struct dmdevice | |
86 | { | |
87 | short dmcsr; /* control status register */ | |
88 | short dmlstat; /* line status register */ | |
89 | short dmpad1[2]; | |
90 | }; | |
91 | ||
92 | /* bits in dm csr */ | |
93 | #define DM_RF 0100000 /* ring flag */ | |
94 | #define DM_CF 0040000 /* carrier flag */ | |
95 | #define DM_CTS 0020000 /* clear to send */ | |
96 | #define DM_SRF 0010000 /* secondary receive flag */ | |
97 | #define DM_CS 0004000 /* clear scan */ | |
98 | #define DM_CM 0002000 /* clear multiplexor */ | |
99 | #define DM_MM 0001000 /* maintenance mode */ | |
100 | #define DM_STP 0000400 /* step */ | |
101 | #define DM_DONE 0000200 /* scanner is done */ | |
102 | #define DM_IE 0000100 /* interrupt enable */ | |
103 | #define DM_SE 0000040 /* scan enable */ | |
104 | #define DM_BUSY 0000020 /* scan busy */ | |
105 | ||
106 | /* bits in dm lsr */ | |
107 | #define DML_RNG 0000200 /* ring */ | |
108 | #define DML_CAR 0000100 /* carrier detect */ | |
109 | #define DML_CTS 0000040 /* clear to send */ | |
110 | #define DML_SR 0000020 /* secondary receive */ | |
111 | #define DML_ST 0000010 /* secondary transmit */ | |
112 | #define DML_RTS 0000004 /* request to send */ | |
113 | #define DML_DTR 0000002 /* data terminal ready */ | |
114 | #define DML_LE 0000001 /* line enable */ | |
115 | ||
116 | #define DML_ON (DML_DTR|DML_LE) | |
117 | #define DML_OFF (DML_LE) | |
a18f326f | 118 | |
a18f326f | 119 | /* |
d4638843 | 120 | * Local variables for the driver |
a18f326f | 121 | */ |
0916e0d1 BJ |
122 | short dhsar[NDH]; /* software copy of last bar */ |
123 | short dhsoftCAR[NDH]; | |
a18f326f | 124 | |
0916e0d1 BJ |
125 | struct tty dh11[NDH*16]; |
126 | int ndh11 = NDH*16; | |
d4638843 BJ |
127 | int dhact; /* mask of active dh's */ |
128 | int dhstart(), ttrstrt(); | |
a18f326f | 129 | |
d4638843 BJ |
130 | /* |
131 | * The clist space is mapped by the driver onto each UNIBUS. | |
132 | * The UBACVT macro converts a clist space address for unibus uban | |
133 | * into an i/o space address for the DMA routine. | |
134 | */ | |
135 | int dh_ubinfo[MAXNUBA]; /* info about allocated unibus map */ | |
136 | int cbase[MAXNUBA]; /* base address in unibus map */ | |
137 | #define UBACVT(x, uban) (cbase[uban] + ((x)-(char *)cfree)) | |
a18f326f | 138 | |
88d5b764 BJ |
139 | /* |
140 | * Routine for configuration to force a dh to interrupt. | |
141 | * Set to transmit at 9600 baud, and cause a transmitter interrupt. | |
142 | */ | |
7e00c42b | 143 | /*ARGSUSED*/ |
71236e46 | 144 | dhprobe(reg) |
3f3a34c3 BJ |
145 | caddr_t reg; |
146 | { | |
7e00c42b | 147 | register int br, cvec; /* these are ``value-result'' */ |
d4638843 | 148 | register struct dhdevice *dhaddr = (struct dhdevice *)reg; |
5aa9d5ea | 149 | |
71236e46 BJ |
150 | #ifdef lint |
151 | br = 0; cvec = br; br = cvec; | |
152 | #endif | |
52ab9b2b | 153 | #ifndef notdef |
7e286c72 BJ |
154 | dhaddr->un.dhcsr = DH_RIE|DH_MM|DH_RI; |
155 | DELAY(5); | |
156 | dhaddr->un.dhcsr = 0; | |
157 | #else | |
88d5b764 BJ |
158 | dhaddr->un.dhcsr = DH_TIE; |
159 | DELAY(5); | |
160 | dhaddr->dhlpr = (B9600 << 10) | (B9600 << 6) | BITS7|PENABLE; | |
5aa9d5ea | 161 | dhaddr->dhbcr = -1; |
5aa9d5ea | 162 | dhaddr->dhcar = 0; |
88d5b764 BJ |
163 | dhaddr->dhbar = 1; |
164 | DELAY(100000); /* wait 1/10'th of a sec for interrupt */ | |
5aa9d5ea | 165 | dhaddr->un.dhcsr = 0; |
88d5b764 BJ |
166 | if (cvec && cvec != 0x200) |
167 | cvec -= 4; /* transmit -> receive */ | |
4afc81c0 | 168 | #endif |
88d5b764 | 169 | return (1); |
3f3a34c3 BJ |
170 | } |
171 | ||
88d5b764 | 172 | /* |
71236e46 | 173 | * Routine called to attach a dh. |
88d5b764 | 174 | */ |
71236e46 | 175 | dhattach(ui) |
b09915c5 | 176 | struct uba_device *ui; |
3f3a34c3 BJ |
177 | { |
178 | ||
7e286c72 | 179 | dhsoftCAR[ui->ui_unit] = ui->ui_flags; |
3f3a34c3 BJ |
180 | } |
181 | ||
d4638843 BJ |
182 | /* |
183 | * Configuration routine to cause a dm to interrupt. | |
184 | */ | |
71236e46 BJ |
185 | dmprobe(reg) |
186 | caddr_t reg; | |
d4638843 BJ |
187 | { |
188 | register int br, vec; /* value-result */ | |
71236e46 | 189 | register struct dmdevice *dmaddr = (struct dmdevice *)reg; |
d4638843 | 190 | |
71236e46 | 191 | #ifdef lint |
a0eab615 | 192 | br = 0; vec = br; br = vec; |
71236e46 | 193 | #endif |
d4638843 BJ |
194 | dmaddr->dmcsr = DM_DONE|DM_IE; |
195 | DELAY(20); | |
196 | dmaddr->dmcsr = 0; | |
71236e46 | 197 | return (1); |
d4638843 BJ |
198 | } |
199 | ||
71236e46 BJ |
200 | /*ARGSUSED*/ |
201 | dmattach(ui) | |
b09915c5 | 202 | struct uba_device *ui; |
d4638843 BJ |
203 | { |
204 | ||
205 | /* no local state to set up */ | |
206 | } | |
207 | ||
a18f326f | 208 | /* |
7e00c42b BJ |
209 | * Open a DH11 line, mapping the clist onto the uba if this |
210 | * is the first dh on this uba. Turn on this dh if this is | |
211 | * the first use of it. Also do a dmopen to wait for carrier. | |
a18f326f BJ |
212 | */ |
213 | /*ARGSUSED*/ | |
214 | dhopen(dev, flag) | |
3f3a34c3 | 215 | dev_t dev; |
a18f326f BJ |
216 | { |
217 | register struct tty *tp; | |
3f3a34c3 | 218 | register int unit, dh; |
d4638843 | 219 | register struct dhdevice *addr; |
b09915c5 | 220 | register struct uba_device *ui; |
a18f326f BJ |
221 | int s; |
222 | ||
3f3a34c3 BJ |
223 | unit = minor(dev); |
224 | dh = unit >> 4; | |
0916e0d1 | 225 | if (unit >= NDH*16 || (ui = dhinfo[dh])== 0 || ui->ui_alive == 0) { |
a18f326f BJ |
226 | u.u_error = ENXIO; |
227 | return; | |
228 | } | |
3f3a34c3 | 229 | tp = &dh11[unit]; |
7e00c42b BJ |
230 | if (tp->t_state&XCLUDE && u.u_uid!=0) { |
231 | u.u_error = EBUSY; | |
232 | return; | |
233 | } | |
d4638843 | 234 | addr = (struct dhdevice *)ui->ui_addr; |
a18f326f BJ |
235 | tp->t_addr = (caddr_t)addr; |
236 | tp->t_oproc = dhstart; | |
237 | tp->t_iproc = NULL; | |
238 | tp->t_state |= WOPEN; | |
7e00c42b BJ |
239 | /* |
240 | * While setting up state for this uba and this dh, | |
241 | * block uba resets which can clear the state. | |
242 | */ | |
243 | s = spl5(); | |
5aa9d5ea | 244 | if (dh_ubinfo[ui->ui_ubanum] == 0) { |
d319892b | 245 | /* 512+ is a kludge to try to get around a hardware problem */ |
3f3a34c3 | 246 | dh_ubinfo[ui->ui_ubanum] = |
5aa9d5ea | 247 | uballoc(ui->ui_ubanum, (caddr_t)cfree, |
4c05b581 | 248 | 512+nclist*sizeof(struct cblock), 0); |
88d5b764 BJ |
249 | cbase[ui->ui_ubanum] = dh_ubinfo[ui->ui_ubanum]&0x3ffff; |
250 | } | |
251 | if ((dhact&(1<<dh)) == 0) { | |
252 | addr->un.dhcsr |= DH_IE; | |
88d5b764 | 253 | dhact |= (1<<dh); |
7e00c42b | 254 | addr->dhsilo = 16; |
a18f326f BJ |
255 | } |
256 | splx(s); | |
7e00c42b BJ |
257 | /* |
258 | * If this is first open, initialze tty state to default. | |
259 | */ | |
a18f326f BJ |
260 | if ((tp->t_state&ISOPEN) == 0) { |
261 | ttychars(tp); | |
87f51a66 | 262 | if (tp->t_ispeed == 0) { |
88d5b764 BJ |
263 | tp->t_ispeed = B300; |
264 | tp->t_ospeed = B300; | |
87f51a66 BJ |
265 | tp->t_flags = ODDP|EVENP|ECHO; |
266 | } | |
3f3a34c3 | 267 | dhparam(unit); |
a18f326f | 268 | } |
7e00c42b BJ |
269 | /* |
270 | * Wait for carrier, then process line discipline specific open. | |
271 | */ | |
a18f326f | 272 | dmopen(dev); |
3f3a34c3 | 273 | (*linesw[tp->t_line].l_open)(dev, tp); |
a18f326f BJ |
274 | } |
275 | ||
276 | /* | |
7e00c42b | 277 | * Close a DH11 line, turning off the DM11. |
a18f326f BJ |
278 | */ |
279 | /*ARGSUSED*/ | |
280 | dhclose(dev, flag) | |
3f3a34c3 BJ |
281 | dev_t dev; |
282 | int flag; | |
a18f326f BJ |
283 | { |
284 | register struct tty *tp; | |
3f3a34c3 | 285 | register unit; |
a18f326f | 286 | |
3f3a34c3 BJ |
287 | unit = minor(dev); |
288 | tp = &dh11[unit]; | |
a18f326f | 289 | (*linesw[tp->t_line].l_close)(tp); |
d4638843 | 290 | ((struct dhdevice *)(tp->t_addr))->dhbreak &= ~(1<<(unit&017)); |
a18f326f | 291 | if (tp->t_state&HUPCLS || (tp->t_state&ISOPEN)==0) |
d4638843 | 292 | dmctl(unit, DML_OFF, DMSET); |
a18f326f BJ |
293 | ttyclose(tp); |
294 | } | |
295 | ||
a18f326f | 296 | dhread(dev) |
3f3a34c3 | 297 | dev_t dev; |
a18f326f | 298 | { |
3f3a34c3 | 299 | register struct tty *tp; |
a18f326f | 300 | |
3f3a34c3 | 301 | tp = &dh11[minor(dev)]; |
a18f326f BJ |
302 | (*linesw[tp->t_line].l_read)(tp); |
303 | } | |
304 | ||
a18f326f | 305 | dhwrite(dev) |
3f3a34c3 | 306 | dev_t dev; |
a18f326f | 307 | { |
3f3a34c3 | 308 | register struct tty *tp; |
a18f326f | 309 | |
3f3a34c3 | 310 | tp = &dh11[minor(dev)]; |
a18f326f BJ |
311 | (*linesw[tp->t_line].l_write)(tp); |
312 | } | |
313 | ||
314 | /* | |
315 | * DH11 receiver interrupt. | |
316 | */ | |
3f3a34c3 BJ |
317 | dhrint(dh) |
318 | int dh; | |
a18f326f BJ |
319 | { |
320 | register struct tty *tp; | |
3f3a34c3 | 321 | register c; |
d4638843 | 322 | register struct dhdevice *addr; |
0e239190 | 323 | register struct tty *tp0; |
b09915c5 | 324 | register struct uba_device *ui; |
b19fe459 | 325 | int overrun = 0; |
a18f326f | 326 | |
3f3a34c3 | 327 | ui = dhinfo[dh]; |
d4638843 BJ |
328 | if (ui == 0 || ui->ui_alive == 0) |
329 | return; | |
330 | addr = (struct dhdevice *)ui->ui_addr; | |
7e00c42b BJ |
331 | tp0 = &dh11[dh<<4]; |
332 | /* | |
333 | * Loop fetching characters from the silo for this | |
334 | * dh until there are no more in the silo. | |
335 | */ | |
336 | while ((c = addr->dhrcr) < 0) { | |
337 | tp = tp0 + ((c>>8)&0xf); | |
338 | if ((tp->t_state&ISOPEN)==0) { | |
a18f326f BJ |
339 | wakeup((caddr_t)tp); |
340 | continue; | |
341 | } | |
7e00c42b | 342 | if (c & DH_PE) |
a18f326f BJ |
343 | if ((tp->t_flags&(EVENP|ODDP))==EVENP |
344 | || (tp->t_flags&(EVENP|ODDP))==ODDP ) | |
345 | continue; | |
b19fe459 BJ |
346 | if ((c & DH_DO) && overrun == 0) { |
347 | printf("dh%d: silo overflow\n", dh); | |
348 | overrun = 1; | |
349 | } | |
7e00c42b BJ |
350 | if (c & DH_FE) |
351 | /* | |
352 | * At framing error (break) generate | |
353 | * a null (in raw mode, for getty), or a | |
354 | * interrupt (in cooked/cbreak mode). | |
355 | */ | |
a18f326f | 356 | if (tp->t_flags&RAW) |
7e00c42b | 357 | c = 0; |
a18f326f | 358 | else |
1c17c385 | 359 | c = tun.t_intrc; |
e2c4935e | 360 | #if NBK > 0 |
5c6adb3e | 361 | if (tp->t_line == NETLDISC) { |
0e239190 | 362 | c &= 0177; |
87f51a66 | 363 | BKINPUT(c, tp); |
0e239190 | 364 | } else |
e2c4935e | 365 | #endif |
7e00c42b | 366 | (*linesw[tp->t_line].l_rint)(c, tp); |
a18f326f BJ |
367 | } |
368 | } | |
369 | ||
370 | /* | |
7e00c42b | 371 | * Ioctl for DH11. |
a18f326f BJ |
372 | */ |
373 | /*ARGSUSED*/ | |
374 | dhioctl(dev, cmd, addr, flag) | |
3f3a34c3 | 375 | caddr_t addr; |
a18f326f BJ |
376 | { |
377 | register struct tty *tp; | |
3f3a34c3 | 378 | register unit = minor(dev); |
a18f326f | 379 | |
3f3a34c3 | 380 | tp = &dh11[unit]; |
038bbe6b | 381 | cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr); |
7e00c42b | 382 | if (cmd == 0) |
038bbe6b | 383 | return; |
f4e18828 | 384 | if (ttioctl(tp, cmd, addr, flag)) { |
7e00c42b | 385 | if (cmd==TIOCSETP || cmd==TIOCSETN) |
3f3a34c3 | 386 | dhparam(unit); |
87f51a66 BJ |
387 | } else switch(cmd) { |
388 | case TIOCSBRK: | |
d4638843 | 389 | ((struct dhdevice *)(tp->t_addr))->dhbreak |= 1<<(unit&017); |
87f51a66 BJ |
390 | break; |
391 | case TIOCCBRK: | |
d4638843 | 392 | ((struct dhdevice *)(tp->t_addr))->dhbreak &= ~(1<<(unit&017)); |
87f51a66 BJ |
393 | break; |
394 | case TIOCSDTR: | |
d4638843 | 395 | dmctl(unit, DML_DTR|DML_RTS, DMBIS); |
87f51a66 BJ |
396 | break; |
397 | case TIOCCDTR: | |
d4638843 | 398 | dmctl(unit, DML_DTR|DML_RTS, DMBIC); |
87f51a66 BJ |
399 | break; |
400 | default: | |
a18f326f | 401 | u.u_error = ENOTTY; |
87f51a66 | 402 | } |
a18f326f BJ |
403 | } |
404 | ||
405 | /* | |
406 | * Set parameters from open or stty into the DH hardware | |
407 | * registers. | |
408 | */ | |
3f3a34c3 BJ |
409 | dhparam(unit) |
410 | register int unit; | |
a18f326f BJ |
411 | { |
412 | register struct tty *tp; | |
d4638843 | 413 | register struct dhdevice *addr; |
3f3a34c3 | 414 | register int lpar; |
0072a3c2 | 415 | int s; |
a18f326f | 416 | |
3f3a34c3 | 417 | tp = &dh11[unit]; |
d4638843 | 418 | addr = (struct dhdevice *)tp->t_addr; |
7e00c42b BJ |
419 | /* |
420 | * Block interrupts so parameters will be set | |
421 | * before the line interrupts. | |
422 | */ | |
0072a3c2 | 423 | s = spl5(); |
7e00c42b | 424 | addr->un.dhcsrl = (unit&0xf) | DH_IE; |
a18f326f BJ |
425 | if ((tp->t_ispeed)==0) { |
426 | tp->t_state |= HUPCLS; | |
d4638843 | 427 | dmctl(unit, DML_OFF, DMSET); |
a18f326f BJ |
428 | return; |
429 | } | |
3f3a34c3 | 430 | lpar = ((tp->t_ospeed)<<10) | ((tp->t_ispeed)<<6); |
7e00c42b | 431 | if ((tp->t_ispeed) == B134) |
3f3a34c3 | 432 | lpar |= BITS6|PENABLE|HDUPLX; |
131b2e17 | 433 | else if ((tp->t_flags&RAW) || (tp->t_local&LLITOUT)) |
3f3a34c3 | 434 | lpar |= BITS8; |
a18f326f | 435 | else |
3f3a34c3 | 436 | lpar |= BITS7|PENABLE; |
a18f326f | 437 | if ((tp->t_flags&EVENP) == 0) |
3f3a34c3 | 438 | lpar |= OPAR; |
7e00c42b | 439 | if ((tp->t_ospeed) == B110) |
3f3a34c3 BJ |
440 | lpar |= TWOSB; |
441 | addr->dhlpr = lpar; | |
0072a3c2 | 442 | splx(s); |
a18f326f BJ |
443 | } |
444 | ||
445 | /* | |
446 | * DH11 transmitter interrupt. | |
447 | * Restart each line which used to be active but has | |
448 | * terminated transmission since the last interrupt. | |
449 | */ | |
3f3a34c3 BJ |
450 | dhxint(dh) |
451 | int dh; | |
a18f326f BJ |
452 | { |
453 | register struct tty *tp; | |
d4638843 | 454 | register struct dhdevice *addr; |
a18f326f | 455 | short ttybit, bar, *sbar; |
b09915c5 | 456 | register struct uba_device *ui; |
7e00c42b | 457 | register int unit; |
71236e46 | 458 | u_short cntr; |
a18f326f | 459 | |
3f3a34c3 | 460 | ui = dhinfo[dh]; |
d4638843 | 461 | addr = (struct dhdevice *)ui->ui_addr; |
88d5b764 BJ |
462 | if (addr->un.dhcsr & DH_NXM) { |
463 | addr->un.dhcsr |= DH_CNI; | |
b19fe459 | 464 | printf("dh%d: NXM\n", dh); |
b4ec79ea | 465 | } |
3f3a34c3 | 466 | sbar = &dhsar[dh]; |
a18f326f | 467 | bar = *sbar & ~addr->dhbar; |
3f3a34c3 | 468 | unit = dh * 16; ttybit = 1; |
7e00c42b BJ |
469 | addr->un.dhcsr &= (short)~DH_TI; |
470 | for (; bar; unit++, ttybit <<= 1) { | |
471 | if (bar & ttybit) { | |
a18f326f BJ |
472 | *sbar &= ~ttybit; |
473 | bar &= ~ttybit; | |
3f3a34c3 | 474 | tp = &dh11[unit]; |
038bbe6b BJ |
475 | tp->t_state &= ~BUSY; |
476 | if (tp->t_state&FLUSH) | |
477 | tp->t_state &= ~FLUSH; | |
478 | else { | |
88d5b764 | 479 | addr->un.dhcsrl = (unit&017)|DH_IE; |
7e00c42b BJ |
480 | /* |
481 | * Do arithmetic in a short to make up | |
482 | * for lost 16&17 bits. | |
483 | */ | |
71236e46 | 484 | cntr = addr->dhcar - |
7e00c42b | 485 | UBACVT(tp->t_outq.c_cf, ui->ui_ubanum); |
a0eab615 | 486 | ndflush(&tp->t_outq, (int)cntr); |
a18f326f | 487 | } |
038bbe6b BJ |
488 | if (tp->t_line) |
489 | (*linesw[tp->t_line].l_start)(tp); | |
490 | else | |
491 | dhstart(tp); | |
a18f326f BJ |
492 | } |
493 | } | |
494 | } | |
495 | ||
496 | /* | |
497 | * Start (restart) transmission on the given DH11 line. | |
498 | */ | |
499 | dhstart(tp) | |
3f3a34c3 | 500 | register struct tty *tp; |
a18f326f | 501 | { |
d4638843 | 502 | register struct dhdevice *addr; |
7e00c42b | 503 | register int car, dh, unit, nch; |
3f3a34c3 | 504 | int s; |
a18f326f | 505 | |
3f3a34c3 BJ |
506 | unit = minor(tp->t_dev); |
507 | dh = unit >> 4; | |
7e00c42b | 508 | unit &= 0xf; |
d4638843 | 509 | addr = (struct dhdevice *)tp->t_addr; |
7e00c42b BJ |
510 | |
511 | /* | |
512 | * Must hold interrupts in following code to prevent | |
513 | * state of the tp from changing. | |
514 | */ | |
515 | s = spl5(); | |
516 | /* | |
517 | * If it's currently active, or delaying, no need to do anything. | |
518 | */ | |
a18f326f BJ |
519 | if (tp->t_state&(TIMEOUT|BUSY|TTSTOP)) |
520 | goto out; | |
7e00c42b BJ |
521 | /* |
522 | * If there are sleepers, and output has drained below low | |
523 | * water mark, wake up the sleepers. | |
524 | */ | |
3f3a34c3 | 525 | if ((tp->t_state&ASLEEP) && tp->t_outq.c_cc<=TTLOWAT(tp)) { |
a18f326f BJ |
526 | tp->t_state &= ~ASLEEP; |
527 | if (tp->t_chan) | |
87f51a66 BJ |
528 | mcstart(tp->t_chan, (caddr_t)&tp->t_outq); |
529 | else | |
a18f326f BJ |
530 | wakeup((caddr_t)&tp->t_outq); |
531 | } | |
7e00c42b BJ |
532 | /* |
533 | * Now restart transmission unless the output queue is | |
534 | * empty. | |
535 | */ | |
a18f326f BJ |
536 | if (tp->t_outq.c_cc == 0) |
537 | goto out; | |
3f3a34c3 | 538 | if (tp->t_flags & RAW) |
a18f326f | 539 | nch = ndqb(&tp->t_outq, 0); |
3f3a34c3 | 540 | else { |
a18f326f | 541 | nch = ndqb(&tp->t_outq, 0200); |
7e00c42b BJ |
542 | /* |
543 | * If first thing on queue is a delay process it. | |
544 | */ | |
a18f326f BJ |
545 | if (nch == 0) { |
546 | nch = getc(&tp->t_outq); | |
7e00c42b | 547 | timeout(ttrstrt, (caddr_t)tp, (nch&0x7f)+6); |
a18f326f BJ |
548 | tp->t_state |= TIMEOUT; |
549 | goto out; | |
550 | } | |
551 | } | |
7e00c42b BJ |
552 | /* |
553 | * If characters to transmit, restart transmission. | |
554 | */ | |
a18f326f | 555 | if (nch) { |
7e00c42b BJ |
556 | car = UBACVT(tp->t_outq.c_cf, dhinfo[dh]->ui_ubanum); |
557 | addr->un.dhcsrl = unit|((car>>12)&0x30)|DH_IE; | |
7e00c42b BJ |
558 | unit = 1 << unit; |
559 | dhsar[dh] |= unit; | |
560 | addr->dhcar = car; | |
a18f326f | 561 | addr->dhbcr = -nch; |
7e00c42b | 562 | addr->dhbar |= unit; |
a18f326f BJ |
563 | tp->t_state |= BUSY; |
564 | } | |
3f3a34c3 | 565 | out: |
a18f326f BJ |
566 | splx(s); |
567 | } | |
568 | ||
a18f326f | 569 | /* |
7e00c42b | 570 | * Stop output on a line, e.g. for ^S/^Q or output flush. |
a18f326f BJ |
571 | */ |
572 | /*ARGSUSED*/ | |
573 | dhstop(tp, flag) | |
7e00c42b | 574 | register struct tty *tp; |
a18f326f | 575 | { |
d4638843 | 576 | register struct dhdevice *addr; |
3f3a34c3 | 577 | register int unit, s; |
a18f326f | 578 | |
d4638843 | 579 | addr = (struct dhdevice *)tp->t_addr; |
7e00c42b BJ |
580 | /* |
581 | * Block input/output interrupts while messing with state. | |
582 | */ | |
583 | s = spl5(); | |
038bbe6b | 584 | if (tp->t_state & BUSY) { |
7e00c42b BJ |
585 | /* |
586 | * Device is transmitting; stop output | |
587 | * by selecting the line and setting the byte | |
588 | * count to -1. We will clean up later | |
589 | * by examining the address where the dh stopped. | |
590 | */ | |
3f3a34c3 | 591 | unit = minor(tp->t_dev); |
88d5b764 | 592 | addr->un.dhcsrl = (unit&017) | DH_IE; |
a18f326f BJ |
593 | if ((tp->t_state&TTSTOP)==0) |
594 | tp->t_state |= FLUSH; | |
038bbe6b BJ |
595 | addr->dhbcr = -1; |
596 | } | |
a18f326f BJ |
597 | splx(s); |
598 | } | |
599 | ||
5c30d566 BJ |
600 | /* |
601 | * Reset state of driver if UBA reset was necessary. | |
602 | * Reset the csrl and lpr registers on open lines, and | |
603 | * restart transmitters. | |
604 | */ | |
3f3a34c3 | 605 | dhreset(uban) |
7e00c42b | 606 | int uban; |
5c30d566 | 607 | { |
3f3a34c3 | 608 | register int dh, unit; |
5c30d566 | 609 | register struct tty *tp; |
b09915c5 | 610 | register struct uba_device *ui; |
5aa9d5ea | 611 | int i; |
5c30d566 | 612 | |
5aa9d5ea RE |
613 | if (dh_ubinfo[uban] == 0) |
614 | return; | |
5aa9d5ea RE |
615 | ubarelse(uban, &dh_ubinfo[uban]); |
616 | dh_ubinfo[uban] = uballoc(uban, (caddr_t)cfree, | |
4c05b581 | 617 | 512+nclist*sizeof (struct cblock), 0); |
5aa9d5ea | 618 | cbase[uban] = dh_ubinfo[uban]&0x3ffff; |
3f3a34c3 | 619 | dh = 0; |
0916e0d1 | 620 | for (dh = 0; dh < NDH; dh++) { |
5aa9d5ea RE |
621 | ui = dhinfo[dh]; |
622 | if (ui == 0 || ui->ui_alive == 0 || ui->ui_ubanum != uban) | |
623 | continue; | |
b19fe459 | 624 | printf(" dh%d", dh); |
d4638843 | 625 | ((struct dhdevice *)ui->ui_addr)->un.dhcsr |= DH_IE; |
d4638843 | 626 | ((struct dhdevice *)ui->ui_addr)->dhsilo = 16; |
5aa9d5ea RE |
627 | unit = dh * 16; |
628 | for (i = 0; i < 16; i++) { | |
629 | tp = &dh11[unit]; | |
630 | if (tp->t_state & (ISOPEN|WOPEN)) { | |
631 | dhparam(unit); | |
d4638843 | 632 | dmctl(unit, DML_ON, DMSET); |
5aa9d5ea RE |
633 | tp->t_state &= ~BUSY; |
634 | dhstart(tp); | |
635 | } | |
636 | unit++; | |
0072a3c2 BJ |
637 | } |
638 | } | |
639 | dhtimer(); | |
5c30d566 | 640 | } |
3f3a34c3 | 641 | |
7e00c42b BJ |
642 | /* |
643 | * At software clock interrupt time or after a UNIBUS reset | |
644 | * empty all the dh silos. | |
645 | */ | |
88d5b764 BJ |
646 | dhtimer() |
647 | { | |
648 | register int dh; | |
649 | ||
0916e0d1 | 650 | for (dh = 0; dh < NDH; dh++) |
88d5b764 BJ |
651 | dhrint(dh); |
652 | } | |
653 | ||
7e00c42b | 654 | /* |
d4638843 | 655 | * Turn on the line associated with dh dev. |
7e00c42b BJ |
656 | */ |
657 | dmopen(dev) | |
658 | dev_t dev; | |
659 | { | |
660 | register struct tty *tp; | |
661 | register struct dmdevice *addr; | |
b09915c5 | 662 | register struct uba_device *ui; |
7e00c42b BJ |
663 | register int unit; |
664 | register int dm; | |
665 | ||
666 | unit = minor(dev); | |
d4638843 | 667 | dm = unit >> 4; |
7e00c42b | 668 | tp = &dh11[unit]; |
7e286c72 | 669 | unit &= 0xf; |
0916e0d1 | 670 | if (dm >= NDH || (ui = dminfo[dm]) == 0 || ui->ui_alive == 0 || |
7e286c72 | 671 | (dhsoftCAR[dm]&(1<<unit))) { |
7e00c42b BJ |
672 | tp->t_state |= CARR_ON; |
673 | return; | |
674 | } | |
675 | addr = (struct dmdevice *)ui->ui_addr; | |
a0eab615 | 676 | (void) spl5(); |
d4638843 BJ |
677 | addr->dmcsr &= ~DM_SE; |
678 | while (addr->dmcsr & DM_BUSY) | |
7e00c42b | 679 | ; |
7e286c72 | 680 | addr->dmcsr = unit; |
d4638843 BJ |
681 | addr->dmlstat = DML_ON; |
682 | if (addr->dmlstat&DML_CAR) | |
7e00c42b | 683 | tp->t_state |= CARR_ON; |
d4638843 | 684 | addr->dmcsr = DH_IE|DM_SE; |
7e00c42b BJ |
685 | while ((tp->t_state&CARR_ON)==0) |
686 | sleep((caddr_t)&tp->t_rawq, TTIPRI); | |
a0eab615 | 687 | (void) spl0(); |
7e00c42b BJ |
688 | } |
689 | ||
690 | /* | |
691 | * Dump control bits into the DM registers. | |
692 | */ | |
693 | dmctl(dev, bits, how) | |
694 | dev_t dev; | |
695 | int bits, how; | |
696 | { | |
b09915c5 | 697 | register struct uba_device *ui; |
7e00c42b BJ |
698 | register struct dmdevice *addr; |
699 | register int unit, s; | |
700 | int dm; | |
701 | ||
702 | unit = minor(dev); | |
703 | dm = unit >> 4; | |
704 | if ((ui = dminfo[dm]) == 0 || ui->ui_alive == 0) | |
705 | return; | |
706 | addr = (struct dmdevice *)ui->ui_addr; | |
707 | s = spl5(); | |
d4638843 BJ |
708 | addr->dmcsr &= ~DM_SE; |
709 | while (addr->dmcsr & DM_BUSY) | |
7e00c42b BJ |
710 | ; |
711 | addr->dmcsr = unit & 0xf; | |
712 | switch(how) { | |
713 | case DMSET: | |
714 | addr->dmlstat = bits; | |
715 | break; | |
716 | case DMBIS: | |
717 | addr->dmlstat |= bits; | |
718 | break; | |
719 | case DMBIC: | |
720 | addr->dmlstat &= ~bits; | |
721 | break; | |
722 | } | |
d4638843 | 723 | addr->dmcsr = DH_IE|DM_SE; |
7e00c42b BJ |
724 | splx(s); |
725 | } | |
726 | ||
727 | /* | |
728 | * DM11 interrupt; deal with carrier transitions. | |
729 | */ | |
730 | dmintr(dm) | |
731 | register int dm; | |
732 | { | |
b09915c5 | 733 | register struct uba_device *ui; |
7e00c42b BJ |
734 | register struct tty *tp; |
735 | register struct dmdevice *addr; | |
736 | ||
737 | ui = dminfo[dm]; | |
d4638843 BJ |
738 | if (ui == 0) |
739 | return; | |
7e00c42b | 740 | addr = (struct dmdevice *)ui->ui_addr; |
d4638843 | 741 | if (addr->dmcsr&DM_DONE && addr->dmcsr&DM_CF) { |
7e00c42b BJ |
742 | tp = &dh11[(dm<<4)+(addr->dmcsr&0xf)]; |
743 | wakeup((caddr_t)&tp->t_rawq); | |
744 | if ((tp->t_state&WOPEN)==0 && | |
745 | (tp->t_local&LMDMBUF)) { | |
d4638843 | 746 | if (addr->dmlstat & DML_CAR) { |
7e00c42b BJ |
747 | tp->t_state &= ~TTSTOP; |
748 | ttstart(tp); | |
749 | } else if ((tp->t_state&TTSTOP) == 0) { | |
750 | tp->t_state |= TTSTOP; | |
751 | dhstop(tp, 0); | |
752 | } | |
d4638843 | 753 | } else if ((addr->dmlstat&DML_CAR)==0) { |
7e00c42b BJ |
754 | if ((tp->t_state&WOPEN)==0 && |
755 | (tp->t_local&LNOHANG)==0) { | |
756 | gsignal(tp->t_pgrp, SIGHUP); | |
757 | gsignal(tp->t_pgrp, SIGCONT); | |
758 | addr->dmlstat = 0; | |
759 | flushtty(tp, FREAD|FWRITE); | |
760 | } | |
761 | tp->t_state &= ~CARR_ON; | |
762 | } else | |
763 | tp->t_state |= CARR_ON; | |
d4638843 | 764 | addr->dmcsr = DH_IE|DM_SE; |
7e00c42b BJ |
765 | } |
766 | } | |
4569bb70 | 767 | #endif |