[unix-history] / usr / src / sys / vax / uba / ubareg.h

/*
 * Copyright (c) 1982, 1986 Regents of the University of California.
 * All rights reserved.  The Berkeley software License Agreement
 * specifies the terms and conditions for redistribution.
 *
 *	@(#)ubareg.h	7.2 (Berkeley) %G%
 */

/*
 * VAX UNIBUS adapter definitions
 */

/*
 * "UNIBUS" adaptor types.
 * This code is used for both UNIBUSes and Q-buses
 * with different types of adaptors.
 * Definition of a type includes support code for that type.
 */
#if VAX780 || VAX8600
#define	DW780	1		/* has adaptor regs, sr: 780/785/8600 */
#endif

#if VAX750
#define	DW750	2		/* has adaptor regs, no sr: 750, 730 */
#endif

#if VAX730
#define	DW730	3		/* has adaptor regs, no sr: 750, 730 */
#endif

#if VAX630
#define	QBA	4		/* 22-bit Q-bus, no adaptor regs: uVAX II */
#endif

#if VAX8200 || VAX8500 || VAX8800
#define	DWBUA	5		/* BI UNIBUS adaptor: 8200/8500/8800 */
#endif

/*
 * Size of unibus memory address space in pages
 * (also number of map registers).
 * QBAPAGES should be 8192, but umem needs to be expanded.
 */
#define	UBAPAGES	496
#define	NUBMREG		496
#define	QBAPAGES	UBAPAGES	/* for now; should be 8192 */
#define	UBAIOPAGES	16

#ifndef LOCORE
/*
 * DW780/DW750 hardware registers
 */
struct uba_regs
{
	int	uba_cnfgr;		/* configuration register */
	int	uba_cr;			/* control register */
	int	uba_sr;			/* status register */
	int	uba_dcr;		/* diagnostic control register */
	int	uba_fmer;		/* failed map entry register */
	int	uba_fubar;		/* failed UNIBUS address register */
	int	pad1[2];
	int	uba_brsvr[4];
	int	uba_brrvr[4];		/* receive vector registers */
	int	uba_dpr[16];		/* buffered data path register */
	int	pad2[480];
	struct	pte uba_map[UBAPAGES];	/* unibus map register */
	int	pad3[UBAIOPAGES];	/* no maps for device address space */
};
#endif

#ifdef DW780
/* uba_cnfgr */
#define	UBACNFGR_UBINIT	0x00040000	/* unibus init asserted */
#define	UBACNFGR_UBPDN	0x00020000	/* unibus power down */
#define	UBACNFGR_UBIC	0x00010000	/* unibus init complete */

#define UBACNFGR_BITS \
"\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"

/* uba_cr */
#define	UBACR_MRD16	0x40000000	/* map reg disable bit 4 */
#define	UBACR_MRD8	0x20000000	/* map reg disable bit 3 */
#define	UBACR_MRD4	0x10000000	/* map reg disable bit 2 */
#define	UBACR_MRD2	0x08000000	/* map reg disable bit 1 */
#define	UBACR_MRD1	0x04000000	/* map reg disable bit 0 */
#define	UBACR_IFS	0x00000040	/* interrupt field switch */
#define	UBACR_BRIE	0x00000020	/* BR interrupt enable */
#define	UBACR_USEFIE	0x00000010	/* UNIBUS to SBI error field IE */
#define	UBACR_SUEFIE	0x00000008	/* SBI to UNIBUS error field IE */
#define	UBACR_CNFIE	0x00000004	/* configuration IE */
#define	UBACR_UPF	0x00000002	/* UNIBUS power fail */
#define	UBACR_ADINIT	0x00000001	/* adapter init */

/* uba_sr */
#define	UBASR_BR7FULL	0x08000000	/* BR7 receive vector reg full */
#define	UBASR_BR6FULL	0x04000000	/* BR6 receive vector reg full */
#define	UBASR_BR5FULL	0x02000000	/* BR5 receive vector reg full */
#define	UBASR_BR4FULL	0x01000000	/* BR4 receive vector reg full */
#define	UBASR_RDTO	0x00000400	/* UNIBUS to SBI read data timeout */
#define	UBASR_RDS	0x00000200	/* read data substitute */
#define	UBASR_CRD	0x00000100	/* corrected read data */
#define	UBASR_CXTER	0x00000080	/* command transmit error */
#define	UBASR_CXTMO	0x00000040	/* command transmit timeout */
#define	UBASR_DPPE	0x00000020	/* data path parity error */
#define	UBASR_IVMR	0x00000010	/* invalid map register */
#define	UBASR_MRPF	0x00000008	/* map register parity failure */
#define	UBASR_LEB	0x00000004	/* lost error */
#define	UBASR_UBSTO	0x00000002	/* UNIBUS select timeout */
#define	UBASR_UBSSYNTO	0x00000001	/* UNIBUS slave sync timeout */

#define	UBASR_BITS \
"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"

/* uba_brrvr[] */
#define	UBABRRVR_AIRI	0x80000000	/* adapter interrupt request */
#define	UBABRRVR_DIV	0x0000ffff	/* device interrupt vector field */
#endif
 
/* uba_dpr */
#ifdef DW780
#define	UBADPR_BNE	0x80000000	/* buffer not empty - purge */
#define	UBADPR_BTE	0x40000000	/* buffer transfer error */
#define	UBADPR_DPF	0x20000000	/* DP function (RO) */
#define	UBADPR_BS	0x007f0000	/* buffer state field */
#define	UBADPR_BUBA	0x0000ffff	/* buffered UNIBUS address */
#define	UBA_PURGE780(uba, bdp) \
    ((uba)->uba_dpr[bdp] |= UBADPR_BNE)
#else
#define UBA_PURGE780(uba, bdp)
#endif
#ifdef DW750
#define	UBADPR_ERROR	0x80000000	/* error occurred */
#define	UBADPR_NXM	0x40000000	/* nxm from memory */
#define	UBADPR_UCE	0x20000000	/* uncorrectable error */
#define	UBADPR_PURGE	0x00000001	/* purge bdp */
/* the DELAY is for a hardware problem */
#define	UBA_PURGE750(uba, bdp) { \
    ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \
    DELAY(8); \
}
#else
#define UBA_PURGE750(uba, bdp)
#endif

/*
 * Macros for fast buffered data path purging in time-critical routines.
 *
 * Too bad C pre-processor doesn't have the power of LISP in macro
 * expansion...
 */

#if DW780 || DW750
#define	UBAPURGE(uba, bdp) { \
	switch (cpu) { \
	case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
	case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
	} \
}
#else
#define	UBAPURGE(uba, bdp)
#endif


/* uba_mr[] */
#define	UBAMR_MRV	0x80000000	/* map register valid */
#define	UBAMR_BO	0x02000000	/* byte offset bit */
#define	UBAMR_DPDB	0x01e00000	/* data path designator field */
#define	UBAMR_SBIPFN	0x000fffff	/* SBI page address field */

#define	UBAMR_DPSHIFT	21		/* shift to data path designator */

/*
 * Number of unibus buffered data paths and possible uba's per cpu type.
 */
#define	NBDP8600	15
#define	NBDP780		15
#define	NBDP750		3
#define	NBDP730		0
#define	MAXNBDP		15

/*
 * Symbolic BUS addresses for UBAs.
 */

#if VAX630
#define	QBAMAP630	((struct pte *)0x20088000)
#define	QMEM630		0x30000000
#define	QIOPAGE630	0x20000000
/*
 * Q-bus control registers
 */
#define	QIPCR		0x1f40		/* from start of iopage */
/* bits in QIPCR */
#define	Q_DBIRQ		0x0001		/* doorbell interrupt request */
#define	Q_LMEAE		0x0020		/* local mem external access enable */
#define	Q_DBIIE		0x0040		/* doorbell interrupt enable */
#define	Q_AUXHLT	0x0100		/* auxiliary processor halt */
#define	Q_DMAQPE	0x8000		/* Q22 bus address space parity error */
#endif

#if VAX730
#define	UMEM730		0xfc0000
#endif

#if VAX750
#define	UMEM750(i)	(0xfc0000-(i)*0x40000)
#endif

#if VAX780
#define	UMEM780(i)	(0x20100000+(i)*0x40000)
#endif

#if VAX8600
#define	UMEMA8600(i)	(0x20100000+(i)*0x40000)
#define	UMEMB8600(i)	(0x22100000+(i)*0x40000)
#endif

/*
 * Macro to offset a UNIBUS device address, often expressed as
 * something like 0172520, by forcing it into the last 8K
 * of UNIBUS memory space.
 */
#define	ubdevreg(addr)	((addr) & 017777)
Commit	Line	Data
da7c5cc6	1	/*
0880b18e	2	* Copyright (c) 1982, 1986 Regents of the University of California.
da7c5cc6 KM	3	* All rights reserved. The Berkeley software License Agreement
	4	* specifies the terms and conditions for redistribution.
	5	*
63503d24	6	* @(#)ubareg.h 7.2 (Berkeley) %G%
da7c5cc6	7	*/
1cb3d36a BJ	8
1cb3d36a BJ	9	/*
63503d24	10	* VAX UNIBUS adapter definitions
1cb3d36a	11	*/
bce08673 JB	12
bce08673 JB	13	/*
63503d24 MK	14	* "UNIBUS" adaptor types.
	15	* This code is used for both UNIBUSes and Q-buses
	16	* with different types of adaptors.
	17	* Definition of a type includes support code for that type.
bce08673	18	*/
63503d24 MK	19	#if VAX780 \|\| VAX8600
	20	#define DW780 1 /* has adaptor regs, sr: 780/785/8600 */
	21	#endif
	22
	23	#if VAX750
	24	#define DW750 2 /* has adaptor regs, no sr: 750, 730 */
	25	#endif
	26
	27	#if VAX730
	28	#define DW730 3 /* has adaptor regs, no sr: 750, 730 */
	29	#endif
	30
	31	#if VAX630
	32	#define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */
	33	#endif
	34
	35	#if VAX8200 \|\| VAX8500 \|\| VAX8800
	36	#define DWBUA 5 /* BI UNIBUS adaptor: 8200/8500/8800 */
	37	#endif
bce08673 JB	38
bce08673 JB	39	/*
63503d24 MK	40	* Size of unibus memory address space in pages
	41	* (also number of map registers).
	42	* QBAPAGES should be 8192, but umem needs to be expanded.
bce08673	43	*/
63503d24 MK	44	#define UBAPAGES 496
	45	#define NUBMREG 496
	46	#define QBAPAGES UBAPAGES /* for now; should be 8192 */
	47	#define UBAIOPAGES 16
bce08673	48
b5fa1937	49	#ifndef LOCORE
1cb3d36a	50	/*
63503d24	51	* DW780/DW750 hardware registers
1cb3d36a	52	*/
1cb3d36a BJ	53	struct uba_regs
1cb3d36a BJ	54	{
bbe0bf68 BJ	55	int uba_cnfgr; /* configuration register */
	56	int uba_cr; /* control register */
	57	int uba_sr; /* status register */
	58	int uba_dcr; /* diagnostic control register */
	59	int uba_fmer; /* failed map entry register */
	60	int uba_fubar; /* failed UNIBUS address register */
1cb3d36a BJ	61	int pad1[2];
1cb3d36a BJ	62	int uba_brsvr[4];
bbe0bf68 BJ	63	int uba_brrvr[4]; /* receive vector registers */
bbe0bf68 BJ	64	int uba_dpr[16]; /* buffered data path register */
1cb3d36a	65	int pad2[480];
63503d24 MK	66	struct pte uba_map[UBAPAGES]; /* unibus map register */
63503d24 MK	67	int pad3[UBAIOPAGES]; /* no maps for device address space */
10a50234	68	};
b5fa1937	69	#endif
10a50234	70
63503d24	71	#ifdef DW780
4df4b0ef BJ	72	/* uba_cnfgr */
	73	#define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
	74	#define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
	75	#define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
	76
44c2d30b MK	77	#define UBACNFGR_BITS \
	78	"\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
	79
4df4b0ef BJ	80	/* uba_cr */
	81	#define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
	82	#define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
	83	#define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
	84	#define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
	85	#define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
	86	#define UBACR_IFS 0x00000040 /* interrupt field switch */
	87	#define UBACR_BRIE 0x00000020 /* BR interrupt enable */
	88	#define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
	89	#define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
	90	#define UBACR_CNFIE 0x00000004 /* configuration IE */
	91	#define UBACR_UPF 0x00000002 /* UNIBUS power fail */
	92	#define UBACR_ADINIT 0x00000001 /* adapter init */
10a50234	93
4df4b0ef BJ	94	/* uba_sr */
	95	#define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
	96	#define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
	97	#define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
	98	#define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
	99	#define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
	100	#define UBASR_RDS 0x00000200 /* read data substitute */
	101	#define UBASR_CRD 0x00000100 /* corrected read data */
	102	#define UBASR_CXTER 0x00000080 /* command transmit error */
	103	#define UBASR_CXTMO 0x00000040 /* command transmit timeout */
	104	#define UBASR_DPPE 0x00000020 /* data path parity error */
	105	#define UBASR_IVMR 0x00000010 /* invalid map register */
	106	#define UBASR_MRPF 0x00000008 /* map register parity failure */
	107	#define UBASR_LEB 0x00000004 /* lost error */
	108	#define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
	109	#define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
f7c4179b BJ	110
	111	#define UBASR_BITS \
	112	"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
10a50234	113
4df4b0ef BJ	114	/* uba_brrvr[] */
	115	#define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
	116	#define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
bce08673	117	#endif
10a50234	118
4df4b0ef	119	/* uba_dpr */
63503d24	120	#ifdef DW780
4df4b0ef BJ	121	#define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
	122	#define UBADPR_BTE 0x40000000 /* buffer transfer error */
	123	#define UBADPR_DPF 0x20000000 /* DP function (RO) */
	124	#define UBADPR_BS 0x007f0000 /* buffer state field */
	125	#define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
b2fc55f0 BJ	126	#define UBA_PURGE780(uba, bdp) \
b2fc55f0 BJ	127	((uba)->uba_dpr[bdp] \|= UBADPR_BNE)
bce08673 JB	128	#else
	129	#define UBA_PURGE780(uba, bdp)
	130	#endif
63503d24	131	#ifdef DW750
4df4b0ef BJ	132	#define UBADPR_ERROR 0x80000000 /* error occurred */
	133	#define UBADPR_NXM 0x40000000 /* nxm from memory */
	134	#define UBADPR_UCE 0x20000000 /* uncorrectable error */
	135	#define UBADPR_PURGE 0x00000001 /* purge bdp */
3b1e560f SL	136	/* the DELAY is for a hardware problem */
	137	#define UBA_PURGE750(uba, bdp) { \
	138	((uba)->uba_dpr[bdp] \|= (UBADPR_PURGE\|UBADPR_NXM\|UBADPR_UCE)); \
	139	DELAY(8); \
	140	}
bce08673 JB	141	#else
	142	#define UBA_PURGE750(uba, bdp)
	143	#endif
	144
114cd253 BJ	145	/*
	146	* Macros for fast buffered data path purging in time-critical routines.
	147	*
	148	* Too bad C pre-processor doesn't have the power of LISP in macro
	149	* expansion...
	150	*/
bce08673	151
63503d24	152	#if DW780 \|\| DW750
114cd253 BJ	153	#define UBAPURGE(uba, bdp) { \
114cd253 BJ	154	switch (cpu) { \
bce08673	155	case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
4c078bb2	156	case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
114cd253 BJ	157	} \
114cd253 BJ	158	}
63503d24	159	#else
23bd9454	160	#define UBAPURGE(uba, bdp)
114cd253 BJ	161	#endif
114cd253 BJ	162
bce08673 JB	163
bce08673 JB	164
4df4b0ef BJ	165	/* uba_mr[] */
	166	#define UBAMR_MRV 0x80000000 /* map register valid */
	167	#define UBAMR_BO 0x02000000 /* byte offset bit */
	168	#define UBAMR_DPDB 0x01e00000 /* data path designator field */
	169	#define UBAMR_SBIPFN 0x000fffff /* SBI page address field */
10a50234	170
4df4b0ef	171	#define UBAMR_DPSHIFT 21 /* shift to data path designator */
10a50234	172
10a50234	173	/*
4df4b0ef	174	* Number of unibus buffered data paths and possible uba's per cpu type.
10a50234	175	*/
bce08673	176	#define NBDP8600 15
63503d24 MK	177	#define NBDP780 15
	178	#define NBDP750 3
	179	#define NBDP730 0
	180	#define MAXNBDP 15
10a50234	181
10a50234	182	/*
bce08673	183	* Symbolic BUS addresses for UBAs.
10a50234	184	*/
bce08673	185
9d2503c6	186	#if VAX630
63503d24 MK	187	#define QBAMAP630 ((struct pte *)0x20088000)
	188	#define QMEM630 0x30000000
	189	#define QIOPAGE630 0x20000000
	190	/*
	191	* Q-bus control registers
	192	*/
	193	#define QIPCR 0x1f40 /* from start of iopage */
	194	/* bits in QIPCR */
	195	#define Q_DBIRQ 0x0001 /* doorbell interrupt request */
	196	#define Q_LMEAE 0x0020 /* local mem external access enable */
	197	#define Q_DBIIE 0x0040 /* doorbell interrupt enable */
	198	#define Q_AUXHLT 0x0100 /* auxiliary processor halt */
	199	#define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */
9d2503c6 BK	200	#endif
9d2503c6 BK	201
10f66600	202	#if VAX730
63503d24	203	#define UMEM730 0xfc0000
ea4d5e21	204	#endif
bce08673	205
4df4b0ef	206	#if VAX750
63503d24	207	#define UMEM750(i) (0xfc0000-(i)*0x40000)
6531d33e	208	#endif
bce08673	209
6531d33e	210	#if VAX780
63503d24	211	#define UMEM780(i) (0x20100000+(i)*0x40000)
b5fa1937	212	#endif
62c8c966	213
bce08673	214	#if VAX8600
63503d24 MK	215	#define UMEMA8600(i) (0x20100000+(i)*0x40000)
63503d24 MK	216	#define UMEMB8600(i) (0x22100000+(i)*0x40000)
bce08673 JB	217	#endif
bce08673 JB	218
62c8c966 BJ	219	/*
62c8c966 BJ	220	* Macro to offset a UNIBUS device address, often expressed as
63503d24 MK	221	* something like 0172520, by forcing it into the last 8K
63503d24 MK	222	* of UNIBUS memory space.
62c8c966	223	*/
63503d24	224	#define ubdevreg(addr) ((addr) & 017777)