[unix-history] / usr / src / sys / vax / uba / vp.c

/*	vp.c	3.2	%H%	*/

#ifdef ERNIE
#include "../h/param.h"
#include "../h/dir.h"
#include "../h/user.h"
#include "../h/buf.h"
#include "../h/systm.h"
#include "../h/map.h"
#include "../h/pte.h"
#include "../h/uba.h"

/*
 * Versatec matrix printer/plotter
 * dma interface driver
 */
int	vpbdp = 1;

unsigned minvpph();

#define	VPPRI	(PZERO-1)

struct	vpregs {
	short	plbcr;
	short	fill;
	short	prbcr;
	unsigned short pbaddr;
	short	plcsr;
	short	plbuf;
	short	prcsr;
	unsigned short prbuf;
};

#define	VPADDR	((struct vpregs *)(UBA0_DEV + 0177500))

#define	ERROR	0100000
#define	DTCINTR	040000
#define	DMAACT	020000
#define	READY	0200
#define	IENABLE	0100
#define	TERMCOM	040
#define	FFCOM	020
#define	EOTCOM	010
#define	CLRCOM	04
#define	RESET	02
#define	SPP	01

struct {
	int	vp_state;
	int	vp_count;
	int	vp_bufp;
} vp11;
int	vp_ubinfo;

struct	buf rvpbuf;

#define	VISOPEN	01
#define	CMNDS	076
#define	MODE	0700
#define	PRINT	0100
#define	PLOT	0200
#define	PPLOT	0400
#define	VBUSY	01000

vpopen()
{

	if (vp11.vp_state & VISOPEN) {
		u.u_error = ENXIO;
		return;
	}
	vp11.vp_state = VISOPEN | PRINT | CLRCOM | RESET;
	vp11.vp_count = 0;
	VPADDR->prcsr = IENABLE | DTCINTR;
	vptimo();
	while (vp11.vp_state & CMNDS) {
		(void) spl4();
		if (vperror(READY)) {
			vpclose();
			u.u_error = EIO;
			return;
		}
		vpstart();
		(void) spl0();
	}
}

vpstrategy(bp)
	register struct buf *bp;
{
	register int e;

	(void) spl4();
	while (vp11.vp_state & VBUSY)
		sleep((caddr_t)&vp11, VPPRI);
	vp11.vp_state |= VBUSY;
	(void) spl0();
	vp_ubinfo = ubasetup(bp, vpbdp);
	vp11.vp_bufp = vp_ubinfo & 0x3ffff;
	(void) spl4();
	if (e = vperror(READY))
		goto brkout;
	vp11.vp_count = bp->b_bcount;
	vpstart();
	while ((vp11.vp_state&PLOT ? VPADDR->plcsr : VPADDR->prcsr) & DMAACT)
		sleep((caddr_t)&vp11, VPPRI);
	vp11.vp_count = 0;
	vp11.vp_bufp = 0;
	if ((vp11.vp_state&MODE) == PPLOT)
		vp11.vp_state = (vp11.vp_state &~ MODE) | PLOT;
	(void) spl0();
brkout:
	ubafree(vp_ubinfo), vp_ubinfo = 0;
	vp11.vp_state &= ~VBUSY;
	iodone(bp);
	if (e)
		u.u_error = EIO;
	wakeup((caddr_t)&vp11);
}

int	vpblock = 16384;

unsigned
minvpph(bp)
struct buf *bp;
{

	if (bp->b_bcount > vpblock)
		bp->b_bcount = vpblock;
}

/*ARGSUSED*/
vpwrite(dev)
{

	physio(vpstrategy, &rvpbuf, dev, B_WRITE, minvpph);
}

vperror(bit)
{
	register int state, e;

	state = vp11.vp_state & PLOT;
	while ((e = (state ? VPADDR->plcsr : VPADDR->prcsr) & (bit|ERROR)) == 0)
		sleep((caddr_t)&vp11, VPPRI);
	return (e & ERROR);
}

vpstart()
{
	register short bit;

	if (vp11.vp_count) {
		VPADDR->pbaddr = vp11.vp_bufp;
		if (vp11.vp_state & (PRINT|PPLOT))
			VPADDR->prbcr = vp11.vp_count;
		else
			VPADDR->plbcr = vp11.vp_count;
		return;
	}
	for (bit = 1; bit != 0; bit <<= 1)
		if (vp11.vp_state&bit&CMNDS) {
			VPADDR->plcsr |= bit;
			vp11.vp_state &= ~bit;
			return;
		}
}

/*ARGSUSED*/
vpioctl(dev, cmd, addr, flag)
	register caddr_t addr;
{
	register int m;

	switch (cmd) {

	case ('v'<<8)+0:
		(void) suword(addr, vp11.vp_state);
		return;

	case ('v'<<8)+1:
		m = fuword(addr);
		if (m == -1) {
			u.u_error = EFAULT;
			return;
		}
		vp11.vp_state = (vp11.vp_state & ~MODE) | (m&(MODE|CMNDS));
		break;

	default:
		u.u_error = ENOTTY;
		return;
	}
	(void) spl4();
	(void) vperror(READY);
	if (vp11.vp_state&PPLOT)
		VPADDR->plcsr |= SPP;
	else
		VPADDR->plcsr &= ~SPP;
	vp11.vp_count = 0;
	while (CMNDS & vp11.vp_state) {
		(void) vperror(READY);
		vpstart();
	}
	(void) spl0();
}

vptimo()
{

	if (vp11.vp_state&VISOPEN)
		timeout(vptimo, (caddr_t)0, HZ/10);
	vpintr(0);
}

/*ARGSUSED*/
vpintr(dev)
{

	wakeup((caddr_t)&vp11);
}

vpclose()
{

	vp11.vp_state = 0;
	vp11.vp_count = 0;
	vp11.vp_bufp = 0;
	VPADDR->plcsr = 0;
}
#endif
Commit	Line	Data
81263dba	1	/* vp.c 3.2 %H% */
2a75a0e9 BJ	2
	3	#ifdef ERNIE
	4	#include "../h/param.h"
	5	#include "../h/dir.h"
	6	#include "../h/user.h"
	7	#include "../h/buf.h"
	8	#include "../h/systm.h"
	9	#include "../h/map.h"
	10	#include "../h/pte.h"
	11	#include "../h/uba.h"
	12
	13	/*
	14	* Versatec matrix printer/plotter
	15	* dma interface driver
	16	*/
	17	int vpbdp = 1;
	18
	19	unsigned minvpph();
	20
	21	#define VPPRI (PZERO-1)
	22
	23	struct vpregs {
	24	short plbcr;
	25	short fill;
	26	short prbcr;
	27	unsigned short pbaddr;
	28	short plcsr;
	29	short plbuf;
	30	short prcsr;
	31	unsigned short prbuf;
	32	};
	33
	34	#define VPADDR ((struct vpregs *)(UBA0_DEV + 0177500))
	35
	36	#define ERROR 0100000
	37	#define DTCINTR 040000
	38	#define DMAACT 020000
	39	#define READY 0200
	40	#define IENABLE 0100
	41	#define TERMCOM 040
	42	#define FFCOM 020
	43	#define EOTCOM 010
	44	#define CLRCOM 04
	45	#define RESET 02
	46	#define SPP 01
	47
	48	struct {
	49	int vp_state;
	50	int vp_count;
	51	int vp_bufp;
	52	} vp11;
	53	int vp_ubinfo;
	54
	55	struct buf rvpbuf;
	56
	57	#define VISOPEN 01
	58	#define CMNDS 076
	59	#define MODE 0700
	60	#define PRINT 0100
	61	#define PLOT 0200
	62	#define PPLOT 0400
	63	#define VBUSY 01000
	64
	65	vpopen()
66	{
67
68	if (vp11.vp_state & VISOPEN) {
69	u.u_error = ENXIO;
70	return;
71	}
72	vp11.vp_state = VISOPEN \| PRINT \| CLRCOM \| RESET;
73	vp11.vp_count = 0;
74	VPADDR->prcsr = IENABLE \| DTCINTR;
75	vptimo();
76	while (vp11.vp_state & CMNDS) {
81263dba	77	(void) spl4();
2a75a0e9 BJ	78	if (vperror(READY)) {
	79	vpclose();
	80	u.u_error = EIO;
	81	return;
	82	}
	83	vpstart();
81263dba	84	(void) spl0();
2a75a0e9 BJ	85	}
	86	}
	87
	88	vpstrategy(bp)
	89	register struct buf *bp;
	90	{
	91	register int e;
	92
81263dba	93	(void) spl4();
2a75a0e9 BJ	94	while (vp11.vp_state & VBUSY)
	95	sleep((caddr_t)&vp11, VPPRI);
	96	vp11.vp_state \|= VBUSY;
81263dba	97	(void) spl0();
2a75a0e9 BJ	98	vp_ubinfo = ubasetup(bp, vpbdp);
2a75a0e9 BJ	99	vp11.vp_bufp = vp_ubinfo & 0x3ffff;
81263dba	100	(void) spl4();
2a75a0e9 BJ	101	if (e = vperror(READY))
	102	goto brkout;
	103	vp11.vp_count = bp->b_bcount;
	104	vpstart();
	105	while ((vp11.vp_state&PLOT ? VPADDR->plcsr : VPADDR->prcsr) & DMAACT)
	106	sleep((caddr_t)&vp11, VPPRI);
	107	vp11.vp_count = 0;
	108	vp11.vp_bufp = 0;
	109	if ((vp11.vp_state&MODE) == PPLOT)
	110	vp11.vp_state = (vp11.vp_state &~ MODE) \| PLOT;
81263dba	111	(void) spl0();
2a75a0e9 BJ	112	brkout:
	113	ubafree(vp_ubinfo), vp_ubinfo = 0;
	114	vp11.vp_state &= ~VBUSY;
	115	iodone(bp);
	116	if (e)
	117	u.u_error = EIO;
	118	wakeup((caddr_t)&vp11);
	119	}
	120
	121	int vpblock = 16384;
	122
	123	unsigned
	124	minvpph(bp)
	125	struct buf *bp;
	126	{
	127
	128	if (bp->b_bcount > vpblock)
	129	bp->b_bcount = vpblock;
	130	}
	131
	132	/ARGSUSED/
	133	vpwrite(dev)
	134	{
	135
	136	physio(vpstrategy, &rvpbuf, dev, B_WRITE, minvpph);
	137	}
	138
	139	vperror(bit)
	140	{
	141	register int state, e;
	142
	143	state = vp11.vp_state & PLOT;
	144	while ((e = (state ? VPADDR->plcsr : VPADDR->prcsr) & (bit\|ERROR)) == 0)
	145	sleep((caddr_t)&vp11, VPPRI);
	146	return (e & ERROR);
	147	}
	148
	149	vpstart()
	150	{
	151	register short bit;
	152
	153	if (vp11.vp_count) {
	154	VPADDR->pbaddr = vp11.vp_bufp;
	155	if (vp11.vp_state & (PRINT\|PPLOT))
	156	VPADDR->prbcr = vp11.vp_count;
	157	else
	158	VPADDR->plbcr = vp11.vp_count;
	159	return;
	160	}
	161	for (bit = 1; bit != 0; bit <<= 1)
	162	if (vp11.vp_state&bit&CMNDS) {
	163	VPADDR->plcsr \|= bit;
	164	vp11.vp_state &= ~bit;
	165	return;
	166	}
	167	}
	168
	169	/ARGSUSED/
	170	vpioctl(dev, cmd, addr, flag)
	171	register caddr_t addr;
	172	{
	173	register int m;
	174
	175	switch (cmd) {
176
177	case ('v'<<8)+0:
81263dba	178	(void) suword(addr, vp11.vp_state);
2a75a0e9 BJ	179	return;
	180
	181	case ('v'<<8)+1:
	182	m = fuword(addr);
	183	if (m == -1) {
	184	u.u_error = EFAULT;
	185	return;
	186	}
	187	vp11.vp_state = (vp11.vp_state & ~MODE) \| (m&(MODE\|CMNDS));
	188	break;
	189
	190	default:
	191	u.u_error = ENOTTY;
	192	return;
	193	}
81263dba BJ	194	(void) spl4();
81263dba BJ	195	(void) vperror(READY);
2a75a0e9 BJ	196	if (vp11.vp_state&PPLOT)
	197	VPADDR->plcsr \|= SPP;
	198	else
	199	VPADDR->plcsr &= ~SPP;
	200	vp11.vp_count = 0;
	201	while (CMNDS & vp11.vp_state) {
81263dba	202	(void) vperror(READY);
2a75a0e9 BJ	203	vpstart();
2a75a0e9 BJ	204	}
81263dba	205	(void) spl0();
2a75a0e9 BJ	206	}
	207
	208	vptimo()
	209	{
	210
	211	if (vp11.vp_state&VISOPEN)
	212	timeout(vptimo, (caddr_t)0, HZ/10);
	213	vpintr(0);
	214	}
	215
	216	/ARGSUSED/
	217	vpintr(dev)
	218	{
	219
	220	wakeup((caddr_t)&vp11);
	221	}
	222
	223	vpclose()
	224	{
	225
	226	vp11.vp_state = 0;
	227	vp11.vp_count = 0;
	228	vp11.vp_bufp = 0;
	229	VPADDR->plcsr = 0;
	230	}
	231	#endif