[unix-history] / .ref-BSD-4_3_Net_2 / usr / src / sys / vax / uba / ubareg.h

/*-
 * Copyright (c) 1982, 1986 The Regents of the University of California.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by the University of
 *	California, Berkeley and its contributors.
 * 4. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)ubareg.h	7.8 (Berkeley) 5/9/91
 */

/*
 * VAX UNIBUS adapter registers
 */

/*
 * "UNIBUS" adaptor types.
 * This code is used for both UNIBUSes and Q-buses
 * with different types of adaptors.
 * Definition of a type includes support code for that type.
 */
#if VAX780 || VAX8600
#define	DW780	1		/* has adaptor regs, sr: 780/785/8600 */
#endif

#if VAX750
#define	DW750	2		/* has adaptor regs, no sr: 750, 730 */
#endif

#if VAX730
#define	DW730	3		/* has adaptor regs, no sr: 750, 730 */
#endif

#if VAX630 || VAX650
#define	QBA	4		/* 22-bit Q-bus, no adaptor regs: uVAX II */
#endif

#if VAX8200 || VAX8500 || VAX8800
#define	DWBUA	5		/* BI UNIBUS adaptor: 8200/8500/8800 */
#endif

/*
 * Size of unibus memory address space in pages
 * (also number of map registers).
 * QBAPAGES should be 8192, but we don't need nearly that much
 * address space, and the return from the allocation routine
 * can accommodate at most 2047 (ubavar.h: UBA_MAXMR);
 * QBAPAGES must be at least UBAPAGES.  Choose pragmatically.
 */
#define	UBAPAGES	496
#define	NUBMREG		496
#if defined(GATEWAY) && !defined(QNIVERT)
#define	QBAPAGES	1024
#else
#define	QBAPAGES	UBAPAGES
#endif
#define	UBAIOADDR	0760000		/* start of I/O page */
#define	UBAIOPAGES	16

#ifndef LOCORE
/*
 * DWBUA hardware registers.
 */
struct dwbua_regs {
	int	pad1[456];		/* actually bii regs + pad */
	int	bua_csr;		/* control and status register */
	int	bua_offset;		/* vector offset register */
	int	bua_fubar;		/* failed UNIBUS address register */
	int	bua_bifar;		/* BI failed address register */
	int	bua_udiag[5];		/* micro diagnostics (R/O) */
	int	pad2[3];
/* dpr[0] is for DDP; dpr's 1 through 5 are for BPD's 1 through 5 */
	int	bua_dpr[6];		/* data path registers */
	int	pad3[10];
	int	bua_bdps[20];		/* buffered data path space *//*???*/
	int	pad4[8];
	struct	pte bua_map[UBAPAGES];	/* unibus map registers */
	int	pad5[UBAIOPAGES];	/* no maps for device address space */
};

#ifdef DWBUA
/* bua_csr */
#define	BUACSR_ERR	0x80000000	/* composite error */
#define	BUACSR_BIF	0x10000000	/* BI failure */
#define	BUACSR_SSYNTO	0x08000000	/* slave sync timeout */
#define	BUACSR_UIE	0x04000000	/* unibus interlock error */
#define	BUACSR_IVMR	0x02000000	/* invalid map register */
#define	BUACSR_BADBDP	0x01000000	/* bad BDP select */
#define	BUACSR_BUAEIE	0x00100000	/* bua error interrupt enable (?) */
#define	BUACSR_UPI	0x00020000	/* unibus power init */
#define	BUACSR_UREGDUMP	0x00010000	/* microdiag register dump */
#define	BUACSR_IERRNO	0x000000ff	/* mask for internal errror number */

/* bua_offset */
#define	BUAOFFSET_MASK	0x00003e00	/* hence max offset = 15872 */

/* bua_dpr */
#define	BUADPR_DPSEL	0x00e00000	/* data path select (?) */
#define	BUADPR_PURGE	0x00000001	/* purge bdp */

/* bua_map -- in particular, those bits that are not in DW780s & DW750s */
#define	BUAMR_IOADR	0x40000000	/* I/O address space */
#define	BUAMR_LAE	0x04000000	/* longword access enable */
	/* I see no reason to use either one, though ... act 6 Aug 1987 */

#define	UBA_PURGEBUA(uba, bdp) \
	(((struct dwbua_regs *)(uba))->bua_dpr[bdp] |= BUADPR_PURGE)
#else
#define	UBA_PURGEBUA(uba, bdp)
#endif

/*
 * DW780/DW750 hardware registers
 */
struct uba_regs {
	int	uba_cnfgr;		/* configuration register */
	int	uba_cr;			/* control register */
	int	uba_sr;			/* status register */
	int	uba_dcr;		/* diagnostic control register */
	int	uba_fmer;		/* failed map entry register */
	int	uba_fubar;		/* failed UNIBUS address register */
	int	pad1[2];
	int	uba_brsvr[4];
	int	uba_brrvr[4];		/* receive vector registers */
	int	uba_dpr[16];		/* buffered data path register */
	int	pad2[480];
	struct	pte uba_map[UBAPAGES];	/* unibus map register */
	int	pad3[UBAIOPAGES];	/* no maps for device address space */
};
#endif

#ifdef DW780
/* uba_cnfgr */
#define	UBACNFGR_UBINIT	0x00040000	/* unibus init asserted */
#define	UBACNFGR_UBPDN	0x00020000	/* unibus power down */
#define	UBACNFGR_UBIC	0x00010000	/* unibus init complete */

#define UBACNFGR_BITS \
"\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"

/* uba_cr */
#define	UBACR_MRD16	0x40000000	/* map reg disable bit 4 */
#define	UBACR_MRD8	0x20000000	/* map reg disable bit 3 */
#define	UBACR_MRD4	0x10000000	/* map reg disable bit 2 */
#define	UBACR_MRD2	0x08000000	/* map reg disable bit 1 */
#define	UBACR_MRD1	0x04000000	/* map reg disable bit 0 */
#define	UBACR_IFS	0x00000040	/* interrupt field switch */
#define	UBACR_BRIE	0x00000020	/* BR interrupt enable */
#define	UBACR_USEFIE	0x00000010	/* UNIBUS to SBI error field IE */
#define	UBACR_SUEFIE	0x00000008	/* SBI to UNIBUS error field IE */
#define	UBACR_CNFIE	0x00000004	/* configuration IE */
#define	UBACR_UPF	0x00000002	/* UNIBUS power fail */
#define	UBACR_ADINIT	0x00000001	/* adapter init */

/* uba_sr */
#define	UBASR_BR7FULL	0x08000000	/* BR7 receive vector reg full */
#define	UBASR_BR6FULL	0x04000000	/* BR6 receive vector reg full */
#define	UBASR_BR5FULL	0x02000000	/* BR5 receive vector reg full */
#define	UBASR_BR4FULL	0x01000000	/* BR4 receive vector reg full */
#define	UBASR_RDTO	0x00000400	/* UNIBUS to SBI read data timeout */
#define	UBASR_RDS	0x00000200	/* read data substitute */
#define	UBASR_CRD	0x00000100	/* corrected read data */
#define	UBASR_CXTER	0x00000080	/* command transmit error */
#define	UBASR_CXTMO	0x00000040	/* command transmit timeout */
#define	UBASR_DPPE	0x00000020	/* data path parity error */
#define	UBASR_IVMR	0x00000010	/* invalid map register */
#define	UBASR_MRPF	0x00000008	/* map register parity failure */
#define	UBASR_LEB	0x00000004	/* lost error */
#define	UBASR_UBSTO	0x00000002	/* UNIBUS select timeout */
#define	UBASR_UBSSYNTO	0x00000001	/* UNIBUS slave sync timeout */

#define	UBASR_BITS \
"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"

/* uba_brrvr[] */
#define	UBABRRVR_AIRI	0x80000000	/* adapter interrupt request */
#define	UBABRRVR_DIV	0x0000ffff	/* device interrupt vector field */
#endif
 
/* uba_dpr */
#ifdef DW780
#define	UBADPR_BNE	0x80000000	/* buffer not empty - purge */
#define	UBADPR_BTE	0x40000000	/* buffer transfer error */
#define	UBADPR_DPF	0x20000000	/* DP function (RO) */
#define	UBADPR_BS	0x007f0000	/* buffer state field */
#define	UBADPR_BUBA	0x0000ffff	/* buffered UNIBUS address */
#define	UBA_PURGE780(uba, bdp) \
    ((uba)->uba_dpr[bdp] |= UBADPR_BNE)
#else
#define UBA_PURGE780(uba, bdp)
#endif
#ifdef DW750
#define	UBADPR_ERROR	0x80000000	/* error occurred */
#define	UBADPR_NXM	0x40000000	/* nxm from memory */
#define	UBADPR_UCE	0x20000000	/* uncorrectable error */
#define	UBADPR_PURGE	0x00000001	/* purge bdp */
/* the DELAY is for a hardware problem */
#define	UBA_PURGE750(uba, bdp) { \
    ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \
    DELAY(8); \
}
#else
#define UBA_PURGE750(uba, bdp)
#endif

/*
 * Macros for fast buffered data path purging in time-critical routines.
 *
 * Too bad C pre-processor doesn't have the power of LISP in macro
 * expansion...
 */

/* THIS IS WRONG, should use pointer to uba_hd */
#if DWBUA || DW780 || DW750
#define	UBAPURGE(uba, bdp) { \
	switch (cpu) { \
	case VAX_8200: UBA_PURGEBUA(uba, bdp); break; \
	case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
	case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
	} \
}
#else
#define	UBAPURGE(uba, bdp)
#endif


/* uba_mr[] */
#define	UBAMR_MRV	0x80000000	/* map register valid */
#define	UBAMR_BO	0x02000000	/* byte offset bit */
#define	UBAMR_DPDB	0x01e00000	/* data path designator field */
#define	UBAMR_SBIPFN	0x001fffff	/* SBI page address field */

#define	UBAMR_DPSHIFT	21		/* shift to data path designator */

/*
 * Number of unibus buffered data paths and possible uba's per cpu type.
 */
#define	NBDP8600	15
#define	NBDP780		15
#define	NBDPBUA		5
#define	NBDP750		3
#define	NBDP730		0
#define	MAXNBDP		15

/*
 * Symbolic BUS addresses for UBAs.
 */

#if VAX630 || VAX650
#define	QBAMAP630	((struct pte *)0x20088000)
#define	QMEM630		0x30000000
#define	QIOPAGE630	0x20000000
/*
 * Q-bus control registers
 */
#define	QIPCR		0x1f40		/* from start of iopage */
/* bits in QIPCR */
#define	Q_DBIRQ		0x0001		/* doorbell interrupt request */
#define	Q_LMEAE		0x0020		/* local mem external access enable */
#define	Q_DBIIE		0x0040		/* doorbell interrupt enable */
#define	Q_AUXHLT	0x0100		/* auxiliary processor halt */
#define	Q_DMAQPE	0x8000		/* Q22 bus address space parity error */
#endif

#if VAX730
#define	UMEM730		0xfc0000
#endif

#if VAX750
#define	UMEM750(i)	(0xfc0000-(i)*0x40000)
#endif

#if VAX780
#define	UMEM780(i)	(0x20100000+(i)*0x40000)
#endif

#if VAX8200		/* BEWARE, argument is node, not ubanum */
#define	UMEM8200(i)	(0x20400000+(i)*0x40000)
#endif

#if VAX8600
#define	UMEMA8600(i)	(0x20100000+(i)*0x40000)
#define	UMEMB8600(i)	(0x22100000+(i)*0x40000)
#endif

/*
 * Macro to offset a UNIBUS device address, often expressed as
 * something like 0172520, by forcing it into the last 8K
 * of UNIBUS memory space.
 */
#define	ubdevreg(addr)	((addr) & 017777)
Commit	Line	Data
af359dea C	1	/*-
	2	* Copyright (c) 1982, 1986 The Regents of the University of California.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions
	7	* are met:
	8	* 1. Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* 2. Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* 3. All advertising materials mentioning features or use of this software
	14	* must display the following acknowledgement:
	15	* This product includes software developed by the University of
	16	* California, Berkeley and its contributors.
	17	* 4. Neither the name of the University nor the names of its contributors
	18	* may be used to endorse or promote products derived from this software
	19	* without specific prior written permission.
	20	*
	21	* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
	22	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	23	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	24	* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
	25	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	26	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	27	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	28	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	29	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	30	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	31	* SUCH DAMAGE.
da7c5cc6	32	*
af359dea	33	* @(#)ubareg.h 7.8 (Berkeley) 5/9/91
da7c5cc6	34	*/
1cb3d36a BJ	35
1cb3d36a BJ	36	/*
b0a4a8c6	37	* VAX UNIBUS adapter registers
1cb3d36a	38	*/
bce08673 JB	39
bce08673 JB	40	/*
63503d24 MK	41	* "UNIBUS" adaptor types.
	42	* This code is used for both UNIBUSes and Q-buses
	43	* with different types of adaptors.
	44	* Definition of a type includes support code for that type.
bce08673	45	*/
63503d24 MK	46	#if VAX780 \|\| VAX8600
	47	#define DW780 1 /* has adaptor regs, sr: 780/785/8600 */
	48	#endif
	49
	50	#if VAX750
	51	#define DW750 2 /* has adaptor regs, no sr: 750, 730 */
	52	#endif
	53
	54	#if VAX730
	55	#define DW730 3 /* has adaptor regs, no sr: 750, 730 */
	56	#endif
	57
f6322301	58	#if VAX630 \|\| VAX650
63503d24 MK	59	#define QBA 4 /* 22-bit Q-bus, no adaptor regs: uVAX II */
	60	#endif
	61
	62	#if VAX8200 \|\| VAX8500 \|\| VAX8800
	63	#define DWBUA 5 /* BI UNIBUS adaptor: 8200/8500/8800 */
	64	#endif
bce08673 JB	65
bce08673 JB	66	/*
63503d24 MK	67	* Size of unibus memory address space in pages
63503d24 MK	68	* (also number of map registers).
b00a6fef MK	69	* QBAPAGES should be 8192, but we don't need nearly that much
	70	* address space, and the return from the allocation routine
	71	* can accommodate at most 2047 (ubavar.h: UBA_MAXMR);
	72	* QBAPAGES must be at least UBAPAGES. Choose pragmatically.
bce08673	73	*/
63503d24 MK	74	#define UBAPAGES 496
63503d24 MK	75	#define NUBMREG 496
b00a6fef MK	76	#if defined(GATEWAY) && !defined(QNIVERT)
b00a6fef MK	77	#define QBAPAGES 1024
8e84596c	78	#else
b00a6fef	79	#define QBAPAGES UBAPAGES
8e84596c	80	#endif
ea457f9f	81	#define UBAIOADDR 0760000 /* start of I/O page */
63503d24	82	#define UBAIOPAGES 16
bce08673	83
b5fa1937	84	#ifndef LOCORE
b0a4a8c6 MK	85	/*
	86	* DWBUA hardware registers.
	87	*/
	88	struct dwbua_regs {
	89	int pad1[456]; /* actually bii regs + pad */
	90	int bua_csr; /* control and status register */
	91	int bua_offset; /* vector offset register */
	92	int bua_fubar; /* failed UNIBUS address register */
	93	int bua_bifar; /* BI failed address register */
	94	int bua_udiag[5]; /* micro diagnostics (R/O) */
	95	int pad2[3];
	96	/* dpr[0] is for DDP; dpr's 1 through 5 are for BPD's 1 through 5 */
	97	int bua_dpr[6]; /* data path registers */
	98	int pad3[10];
	99	int bua_bdps[20]; /* buffered data path space //???*/
	100	int pad4[8];
	101	struct pte bua_map[UBAPAGES]; /* unibus map registers */
	102	int pad5[UBAIOPAGES]; /* no maps for device address space */
	103	};
	104
	105	#ifdef DWBUA
	106	/* bua_csr */
	107	#define BUACSR_ERR 0x80000000 /* composite error */
	108	#define BUACSR_BIF 0x10000000 /* BI failure */
	109	#define BUACSR_SSYNTO 0x08000000 /* slave sync timeout */
	110	#define BUACSR_UIE 0x04000000 /* unibus interlock error */
	111	#define BUACSR_IVMR 0x02000000 /* invalid map register */
	112	#define BUACSR_BADBDP 0x01000000 /* bad BDP select */
	113	#define BUACSR_BUAEIE 0x00100000 /* bua error interrupt enable (?) */
	114	#define BUACSR_UPI 0x00020000 /* unibus power init */
	115	#define BUACSR_UREGDUMP 0x00010000 /* microdiag register dump */
	116	#define BUACSR_IERRNO 0x000000ff /* mask for internal errror number */
	117
	118	/* bua_offset */
	119	#define BUAOFFSET_MASK 0x00003e00 /* hence max offset = 15872 */
	120
	121	/* bua_dpr */
	122	#define BUADPR_DPSEL 0x00e00000 /* data path select (?) */
	123	#define BUADPR_PURGE 0x00000001 /* purge bdp */
	124
	125	/* bua_map -- in particular, those bits that are not in DW780s & DW750s */
	126	#define BUAMR_IOADR 0x40000000 /* I/O address space */
	127	#define BUAMR_LAE 0x04000000 /* longword access enable */
	128	/* I see no reason to use either one, though ... act 6 Aug 1987 */
	129
	130	#define UBA_PURGEBUA(uba, bdp) \
	131	(((struct dwbua_regs *)(uba))->bua_dpr[bdp] \|= BUADPR_PURGE)
	132	#else
	133	#define UBA_PURGEBUA(uba, bdp)
	134	#endif
	135
1cb3d36a	136	/*
63503d24	137	* DW780/DW750 hardware registers
1cb3d36a	138	*/
b0a4a8c6	139	struct uba_regs {
bbe0bf68 BJ	140	int uba_cnfgr; /* configuration register */
	141	int uba_cr; /* control register */
	142	int uba_sr; /* status register */
	143	int uba_dcr; /* diagnostic control register */
	144	int uba_fmer; /* failed map entry register */
	145	int uba_fubar; /* failed UNIBUS address register */
1cb3d36a BJ	146	int pad1[2];
1cb3d36a BJ	147	int uba_brsvr[4];
bbe0bf68 BJ	148	int uba_brrvr[4]; /* receive vector registers */
bbe0bf68 BJ	149	int uba_dpr[16]; /* buffered data path register */
1cb3d36a	150	int pad2[480];
63503d24 MK	151	struct pte uba_map[UBAPAGES]; /* unibus map register */
63503d24 MK	152	int pad3[UBAIOPAGES]; /* no maps for device address space */
10a50234	153	};
b5fa1937	154	#endif
10a50234	155
63503d24	156	#ifdef DW780
4df4b0ef BJ	157	/* uba_cnfgr */
	158	#define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
	159	#define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
	160	#define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
	161
44c2d30b MK	162	#define UBACNFGR_BITS \
	163	"\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC"
	164
4df4b0ef BJ	165	/* uba_cr */
	166	#define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
	167	#define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
	168	#define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
	169	#define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
	170	#define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
	171	#define UBACR_IFS 0x00000040 /* interrupt field switch */
	172	#define UBACR_BRIE 0x00000020 /* BR interrupt enable */
	173	#define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
	174	#define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
	175	#define UBACR_CNFIE 0x00000004 /* configuration IE */
	176	#define UBACR_UPF 0x00000002 /* UNIBUS power fail */
	177	#define UBACR_ADINIT 0x00000001 /* adapter init */
10a50234	178
4df4b0ef BJ	179	/* uba_sr */
	180	#define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
	181	#define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
	182	#define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
	183	#define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
	184	#define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
	185	#define UBASR_RDS 0x00000200 /* read data substitute */
	186	#define UBASR_CRD 0x00000100 /* corrected read data */
	187	#define UBASR_CXTER 0x00000080 /* command transmit error */
	188	#define UBASR_CXTMO 0x00000040 /* command transmit timeout */
	189	#define UBASR_DPPE 0x00000020 /* data path parity error */
	190	#define UBASR_IVMR 0x00000010 /* invalid map register */
	191	#define UBASR_MRPF 0x00000008 /* map register parity failure */
	192	#define UBASR_LEB 0x00000004 /* lost error */
	193	#define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
	194	#define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
f7c4179b BJ	195
	196	#define UBASR_BITS \
	197	"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
10a50234	198
4df4b0ef BJ	199	/* uba_brrvr[] */
	200	#define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
	201	#define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
bce08673	202	#endif
10a50234	203
4df4b0ef	204	/* uba_dpr */
63503d24	205	#ifdef DW780
4df4b0ef BJ	206	#define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
	207	#define UBADPR_BTE 0x40000000 /* buffer transfer error */
	208	#define UBADPR_DPF 0x20000000 /* DP function (RO) */
	209	#define UBADPR_BS 0x007f0000 /* buffer state field */
	210	#define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
b2fc55f0 BJ	211	#define UBA_PURGE780(uba, bdp) \
b2fc55f0 BJ	212	((uba)->uba_dpr[bdp] \|= UBADPR_BNE)
bce08673 JB	213	#else
	214	#define UBA_PURGE780(uba, bdp)
	215	#endif
63503d24	216	#ifdef DW750
4df4b0ef BJ	217	#define UBADPR_ERROR 0x80000000 /* error occurred */
	218	#define UBADPR_NXM 0x40000000 /* nxm from memory */
	219	#define UBADPR_UCE 0x20000000 /* uncorrectable error */
	220	#define UBADPR_PURGE 0x00000001 /* purge bdp */
3b1e560f SL	221	/* the DELAY is for a hardware problem */
	222	#define UBA_PURGE750(uba, bdp) { \
	223	((uba)->uba_dpr[bdp] \|= (UBADPR_PURGE\|UBADPR_NXM\|UBADPR_UCE)); \
	224	DELAY(8); \
	225	}
bce08673 JB	226	#else
	227	#define UBA_PURGE750(uba, bdp)
	228	#endif
	229
114cd253 BJ	230	/*
	231	* Macros for fast buffered data path purging in time-critical routines.
	232	*
	233	* Too bad C pre-processor doesn't have the power of LISP in macro
	234	* expansion...
	235	*/
bce08673	236
b0a4a8c6 MK	237	/* THIS IS WRONG, should use pointer to uba_hd */
b0a4a8c6 MK	238	#if DWBUA \|\| DW780 \|\| DW750
114cd253 BJ	239	#define UBAPURGE(uba, bdp) { \
114cd253 BJ	240	switch (cpu) { \
b0a4a8c6	241	case VAX_8200: UBA_PURGEBUA(uba, bdp); break; \
bce08673	242	case VAX_8600: case VAX_780: UBA_PURGE780((uba), (bdp)); break; \
4c078bb2	243	case VAX_750: UBA_PURGE750((uba), (bdp)); break; \
114cd253 BJ	244	} \
114cd253 BJ	245	}
63503d24	246	#else
23bd9454	247	#define UBAPURGE(uba, bdp)
114cd253 BJ	248	#endif
114cd253 BJ	249
bce08673 JB	250
bce08673 JB	251
4df4b0ef BJ	252	/* uba_mr[] */
	253	#define UBAMR_MRV 0x80000000 /* map register valid */
	254	#define UBAMR_BO 0x02000000 /* byte offset bit */
	255	#define UBAMR_DPDB 0x01e00000 /* data path designator field */
b0a4a8c6	256	#define UBAMR_SBIPFN 0x001fffff /* SBI page address field */
10a50234	257
4df4b0ef	258	#define UBAMR_DPSHIFT 21 /* shift to data path designator */
10a50234	259
10a50234	260	/*
4df4b0ef	261	* Number of unibus buffered data paths and possible uba's per cpu type.
10a50234	262	*/
bce08673	263	#define NBDP8600 15
63503d24	264	#define NBDP780 15
b0a4a8c6	265	#define NBDPBUA 5
63503d24 MK	266	#define NBDP750 3
	267	#define NBDP730 0
	268	#define MAXNBDP 15
10a50234	269
10a50234	270	/*
bce08673	271	* Symbolic BUS addresses for UBAs.
10a50234	272	*/
bce08673	273
f6322301	274	#if VAX630 \|\| VAX650
63503d24 MK	275	#define QBAMAP630 ((struct pte *)0x20088000)
	276	#define QMEM630 0x30000000
	277	#define QIOPAGE630 0x20000000
	278	/*
	279	* Q-bus control registers
	280	*/
	281	#define QIPCR 0x1f40 /* from start of iopage */
	282	/* bits in QIPCR */
	283	#define Q_DBIRQ 0x0001 /* doorbell interrupt request */
	284	#define Q_LMEAE 0x0020 /* local mem external access enable */
	285	#define Q_DBIIE 0x0040 /* doorbell interrupt enable */
	286	#define Q_AUXHLT 0x0100 /* auxiliary processor halt */
	287	#define Q_DMAQPE 0x8000 /* Q22 bus address space parity error */
9d2503c6 BK	288	#endif
9d2503c6 BK	289
10f66600	290	#if VAX730
63503d24	291	#define UMEM730 0xfc0000
ea4d5e21	292	#endif
bce08673	293
4df4b0ef	294	#if VAX750
63503d24	295	#define UMEM750(i) (0xfc0000-(i)*0x40000)
6531d33e	296	#endif
bce08673	297
6531d33e	298	#if VAX780
63503d24	299	#define UMEM780(i) (0x20100000+(i)*0x40000)
b5fa1937	300	#endif
62c8c966	301
b0a4a8c6 MK	302	#if VAX8200 /* BEWARE, argument is node, not ubanum */
	303	#define UMEM8200(i) (0x20400000+(i)*0x40000)
	304	#endif
	305
bce08673	306	#if VAX8600
63503d24 MK	307	#define UMEMA8600(i) (0x20100000+(i)*0x40000)
63503d24 MK	308	#define UMEMB8600(i) (0x22100000+(i)*0x40000)
bce08673 JB	309	#endif
bce08673 JB	310
62c8c966 BJ	311	/*
62c8c966 BJ	312	* Macro to offset a UNIBUS device address, often expressed as
63503d24 MK	313	* something like 0172520, by forcing it into the last 8K
63503d24 MK	314	* of UNIBUS memory space.
62c8c966	315	*/
63503d24	316	#define ubdevreg(addr) ((addr) & 017777)