Commit | Line | Data |
---|---|---|
9893f627 DR |
1 | # |
2 | /* | |
3 | */ | |
4 | ||
5 | /* | |
6 | * GP DR11C driver used for C/A/T | |
7 | */ | |
8 | ||
9 | #include "../param.h" | |
10 | #include "../user.h" | |
11 | #include "../tty.h" | |
12 | ||
13 | #define CATADDR 0167750 | |
14 | #define PCAT 9 | |
15 | #define CATHIWAT 60 | |
16 | #define CATLOWAT 15 | |
17 | ||
18 | struct { | |
19 | int catlock; | |
20 | struct clist oq; | |
21 | } cat; | |
22 | ||
23 | struct { | |
24 | int catcsr; | |
25 | int catbuf; | |
26 | }; | |
27 | ||
28 | ctopen(dev) | |
29 | { | |
30 | if (cat.catlock==0) { | |
31 | cat.catlock++; | |
32 | CATADDR->catcsr =| IENABLE; | |
33 | } else | |
34 | u.u_error = ENXIO; | |
35 | } | |
36 | ||
37 | ctclose() | |
38 | { | |
39 | cat.catlock = 0; | |
40 | } | |
41 | ||
42 | ctwrite(dev) | |
43 | { | |
44 | register c; | |
45 | extern lbolt; | |
46 | ||
47 | while ((c=cpass()) >= 0) { | |
48 | spl5(); | |
49 | while (cat.oq.c_cc > CATHIWAT) | |
50 | sleep(&cat.oq, PCAT); | |
51 | while (putc(c, &cat.oq) < 0) | |
52 | sleep(&lbolt, PCAT); | |
53 | catintr(); | |
54 | spl0(); | |
55 | } | |
56 | } | |
57 | ||
58 | catintr() | |
59 | { | |
60 | register int c; | |
61 | ||
62 | if (CATADDR->catcsr&DONE && (c=getc(&cat.oq))>=0) { | |
63 | CATADDR->catbuf = c; | |
64 | if (cat.oq.c_cc==0 || cat.oq.c_cc==CATLOWAT) | |
65 | wakeup(&cat.oq); | |
66 | } else { | |
67 | if (cat.catlock==0) | |
68 | CATADDR->catcsr = 0; | |
69 | } | |
70 | } |