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bdc5e0ad | 1 | /* |
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2 | * Copyright (c) 1992, 1993 |
3 | * The Regents of the University of California. All rights reserved. | |
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4 | * |
5 | * This software was developed by the Computer Systems Engineering group | |
6 | * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and | |
7 | * contributed to Berkeley. | |
8 | * | |
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9 | * All advertising materials mentioning features or use of this software |
10 | * must display the following acknowledgement: | |
11 | * This product includes software developed by the University of | |
1869bdc0 | 12 | * California, Lawrence Berkeley Laboratory. |
b480239a | 13 | * |
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14 | * Redistribution and use in source and binary forms, with or without |
15 | * modification, are permitted provided that the following conditions | |
16 | * are met: | |
17 | * 1. Redistributions of source code must retain the above copyright | |
18 | * notice, this list of conditions and the following disclaimer. | |
19 | * 2. Redistributions in binary form must reproduce the above copyright | |
20 | * notice, this list of conditions and the following disclaimer in the | |
21 | * documentation and/or other materials provided with the distribution. | |
22 | * 3. All advertising materials mentioning features or use of this software | |
23 | * must display the following acknowledgement: | |
24 | * This product includes software developed by the University of | |
25 | * California, Berkeley and its contributors. | |
26 | * 4. Neither the name of the University nor the names of its contributors | |
27 | * may be used to endorse or promote products derived from this software | |
28 | * without specific prior written permission. | |
29 | * | |
30 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND | |
31 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
33 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | |
34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
36 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
37 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
38 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
39 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
40 | * SUCH DAMAGE. | |
bdc5e0ad | 41 | * |
ad787160 | 42 | * @(#)trap.h 8.1 (Berkeley) 6/11/93 |
bdc5e0ad | 43 | * |
1869bdc0 | 44 | * from: $Header: trap.h,v 1.9 92/11/26 02:04:47 torek Exp $ |
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45 | */ |
46 | ||
47 | #ifndef _MACHINE_TRAP_H | |
48 | #define _MACHINE_TRAP_H | |
49 | /* | |
50 | * | |
51 | * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits | |
52 | * of the trap vector table. The next eight bits are supplied by the | |
53 | * hardware when the trap occurs, and the bottom four bits are always | |
54 | * zero (so that we can shove up to 16 bytes of executable code---exactly | |
55 | * four instructions---into each trap vector). | |
56 | * | |
57 | * The hardware allocates half the trap vectors to hardware and half to | |
58 | * software. | |
59 | * | |
60 | * Traps have priorities assigned (lower number => higher priority). | |
61 | */ | |
62 | ||
63 | #if defined(KERNEL) && !defined(LOCORE) | |
64 | struct trapvec { | |
65 | int tv_instr[4]; /* the four instructions */ | |
66 | }; | |
67 | extern struct trapvec trapbase[256]; /* the 256 vectors */ | |
68 | #endif | |
69 | ||
70 | /* trap vec (pri) description */ | |
71 | #define T_RESET 0x00 /* (1) not actually vectored; jumps to 0 */ | |
72 | #define T_TEXTFAULT 0x01 /* (2) address fault during instr fetch */ | |
73 | #define T_ILLINST 0x02 /* (3) illegal instruction */ | |
74 | #define T_PRIVINST 0x03 /* (4) privileged instruction */ | |
75 | #define T_FPDISABLED 0x04 /* (5) fp instr while fp disabled */ | |
76 | #define T_WINOF 0x05 /* (6) register window overflow */ | |
77 | #define T_WINUF 0x06 /* (7) register window underflow */ | |
78 | #define T_ALIGN 0x07 /* (8) address not properly aligned */ | |
79 | #define T_FPE 0x08 /* (9) floating point exception */ | |
80 | #define T_DATAFAULT 0x09 /* (10) address fault during data fetch */ | |
81 | #define T_TAGOF 0x0a /* (11) tag overflow */ | |
82 | /* 0x0b unused */ | |
83 | /* 0x0c unused */ | |
84 | /* 0x0d unused */ | |
85 | /* 0x0e unused */ | |
86 | /* 0x0f unused */ | |
87 | /* 0x10 unused */ | |
88 | #define T_L1INT 0x11 /* (27) level 1 interrupt */ | |
89 | #define T_L2INT 0x12 /* (26) level 2 interrupt */ | |
90 | #define T_L3INT 0x13 /* (25) level 3 interrupt */ | |
91 | #define T_L4INT 0x14 /* (24) level 4 interrupt */ | |
92 | #define T_L5INT 0x15 /* (23) level 5 interrupt */ | |
93 | #define T_L6INT 0x16 /* (22) level 6 interrupt */ | |
94 | #define T_L7INT 0x17 /* (21) level 7 interrupt */ | |
95 | #define T_L8INT 0x18 /* (20) level 8 interrupt */ | |
96 | #define T_L9INT 0x19 /* (19) level 9 interrupt */ | |
97 | #define T_L10INT 0x1a /* (18) level 10 interrupt */ | |
98 | #define T_L11INT 0x1b /* (17) level 11 interrupt */ | |
99 | #define T_L12INT 0x1c /* (16) level 12 interrupt */ | |
100 | #define T_L13INT 0x1d /* (15) level 13 interrupt */ | |
101 | #define T_L14INT 0x1e /* (14) level 14 interrupt */ | |
102 | #define T_L15INT 0x1f /* (13) level 15 interrupt */ | |
103 | /* 0x20 unused */ | |
104 | /* through 0x23 unused */ | |
105 | #define T_CPDISABLED 0x24 /* (5) coprocessor instr while disabled */ | |
106 | /* 0x25 unused */ | |
107 | /* through 0x27 unused */ | |
108 | #define T_CPEXCEPTION 0x28 /* (9) coprocessor exception */ | |
109 | /* 0x29 unused */ | |
110 | /* through 0x7f unused */ | |
111 | ||
112 | /* beginning of `user' vectors (from trap instructions) - all priority 12 */ | |
113 | #define T_SUN_SYSCALL 0x80 /* system call */ | |
114 | #define T_BREAKPOINT 0x81 /* breakpoint `instruction' */ | |
115 | #define T_DIV0 0x82 /* division routine was handed 0 */ | |
116 | #define T_FLUSHWIN 0x83 /* flush windows */ | |
117 | #define T_CLEANWIN 0x84 /* provide clean windows */ | |
118 | #define T_RANGECHECK 0x85 /* ? */ | |
119 | #define T_FIXALIGN 0x86 /* fix up unaligned accesses */ | |
120 | #define T_INTOF 0x87 /* integer overflow ? */ | |
121 | #define T_KGDB_EXEC 0x88 /* for kernel gdb */ | |
122 | #define T_BSD_SYSCALL 0x89 /* BSD system call */ | |
123 | ||
124 | /* 0x8a..0xff are currently unallocated */ | |
125 | ||
126 | #ifdef KERNEL /* pseudo traps for locore.s */ | |
127 | #define T_RWRET -1 /* need first user window for trap return */ | |
128 | #define T_AST -2 /* no-op, just needed reschedule or profile */ | |
129 | #endif | |
130 | ||
131 | /* flags to system call (flags in %g1 along with syscall number) */ | |
132 | #define SYSCALL_G2RFLAG 0x400 /* on success, return to %g2 rather than npc */ | |
133 | #define SYSCALL_G7RFLAG 0x800 /* use %g7 as above (deprecated) */ | |
134 | ||
135 | /* | |
136 | * `software trap' macros to keep people happy (sparc v8 manual says not | |
137 | * to set the upper bits). | |
138 | */ | |
139 | #define ST_BREAKPOINT (T_BREAKPOINT & 0x7f) | |
140 | #define ST_DIV0 (T_DIV0 & 0x7f) | |
141 | #define ST_FLUSHWIN (T_FLUSHWIN & 0x7f) | |
142 | #define ST_SYSCALL (T_BSD_SYSCALL & 0x7f) | |
143 | ||
144 | #endif /* _MACHINE_TRAP_H_ */ |