Commit | Line | Data |
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f7c4179b | 1 | /* ubareg.h 4.16 81/03/06 */ |
1cb3d36a BJ |
2 | |
3 | /* | |
15b39647 | 4 | * UNIBUS adaptor |
1cb3d36a | 5 | */ |
ca89a8ee BJ |
6 | #if VAX750 |
7 | #define UBA750 ((struct uba_regs *)0xf30000) | |
8 | #define UMEM750 ((u_short *)0xfc0000) | |
9 | #endif | |
1cb3d36a | 10 | |
b5fa1937 | 11 | #ifndef LOCORE |
1cb3d36a BJ |
12 | /* |
13 | * UBA registers | |
14 | */ | |
1cb3d36a BJ |
15 | struct uba_regs |
16 | { | |
bbe0bf68 BJ |
17 | int uba_cnfgr; /* configuration register */ |
18 | int uba_cr; /* control register */ | |
19 | int uba_sr; /* status register */ | |
20 | int uba_dcr; /* diagnostic control register */ | |
21 | int uba_fmer; /* failed map entry register */ | |
22 | int uba_fubar; /* failed UNIBUS address register */ | |
1cb3d36a BJ |
23 | int pad1[2]; |
24 | int uba_brsvr[4]; | |
bbe0bf68 BJ |
25 | int uba_brrvr[4]; /* receive vector registers */ |
26 | int uba_dpr[16]; /* buffered data path register */ | |
1cb3d36a | 27 | int pad2[480]; |
bbe0bf68 BJ |
28 | struct pte uba_map[496]; /* unibus map register */ |
29 | int pad3[16]; /* no maps for device address space */ | |
10a50234 | 30 | }; |
b5fa1937 | 31 | #endif |
10a50234 | 32 | |
b9b45ab9 | 33 | #if VAX780 |
10a50234 BJ |
34 | /* UBA control register, UBACR */ |
35 | #define UBA_MRD16 0x40000000 /* map reg disable bit 4 */ | |
36 | #define UBA_MRD8 0x20000000 /* map reg disable bit 3 */ | |
37 | #define UBA_MRD4 0x10000000 /* map reg disable bit 2 */ | |
38 | #define UBA_MRD2 0x08000000 /* map reg disable bit 1 */ | |
39 | #define UBA_MRD1 0x04000000 /* map reg disable bit 0 */ | |
40 | #define UBA_IFS 0x00000040 /* interrupt field switch */ | |
41 | #define UBA_BRIE 0x00000020 /* BR interrupt enable */ | |
42 | #define UBA_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */ | |
43 | #define UBA_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */ | |
44 | #define UBA_CNFIE 0x00000004 /* configuration IE */ | |
45 | #define UBA_UPF 0x00000002 /* UNIBUS power fail */ | |
46 | #define UBA_ADINIT 0x00000001 /* adapter init */ | |
47 | ||
48 | /* UBA status register, UASR */ | |
49 | #define UBA_BR7FULL 0x08000000 /* BR7 receive vector reg full */ | |
50 | #define UBA_BR6FULL 0x04000000 /* BR6 receive vector reg full */ | |
51 | #define UBA_BR5FULL 0x02000000 /* BR5 receive vector reg full */ | |
52 | #define UBA_BR4FULL 0x01000000 /* BR4 receive vector reg full */ | |
53 | #define UBA_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */ | |
54 | #define UBA_RDS 0x00000200 /* read data substitute */ | |
55 | #define UBA_CRD 0x00000100 /* corrected read data */ | |
56 | #define UBA_CXTER 0x00000080 /* command transmit error */ | |
57 | #define UBA_CXTMO 0x00000040 /* command transmit timeout */ | |
58 | #define UBA_DPPE 0x00000020 /* data path parity error */ | |
59 | #define UBA_IVMR 0x00000010 /* invalid map register */ | |
60 | #define UBA_MRPF 0x00000008 /* map register parity failure */ | |
61 | #define UBA_LEB 0x00000004 /* lost error */ | |
62 | #define UBA_UBSTO 0x00000002 /* UNIBUS select timeout */ | |
f7c4179b BJ |
63 | #define UBA_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */ |
64 | ||
65 | #define UBASR_BITS \ | |
66 | "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO" | |
10a50234 BJ |
67 | |
68 | /* BR receive vector register, BRRVR */ | |
69 | #define UBA_AIRI 0x80000000 /* adapter interrupt request */ | |
70 | #define UBA_DIV 0x0000ffff /* device interrupt vector field */ | |
71 | #endif | |
72 | ||
73 | /* data path register, DPR */ | |
74 | #if VAX780 | |
75 | #define UBA_BNE 0x80000000 /* buffer not empty - purge */ | |
76 | #define UBA_BTE 0x40000000 /* buffer transfer error */ | |
77 | #define UBA_DPF 0x20000000 /* DP function (RO) */ | |
78 | #define UBA_BS 0x007f0000 /* buffer state field */ | |
79 | #define UBA_BUBA 0x0000ffff /* buffered UNIBUS address */ | |
80 | #endif | |
81 | #if VAX750 | |
bbe0bf68 BJ |
82 | #define UBA_ERROR 0x80000000 /* error occurred */ |
83 | #define UBA_NXM 0x40000000 /* nxm from memory */ | |
84 | #define UBA_UCE 0x20000000 /* uncorrectable error */ | |
85 | #define UBA_PURGE 0x00000001 /* purge bdp */ | |
10a50234 BJ |
86 | #endif |
87 | ||
88 | /* map register, MR */ | |
89 | #define UBA_MRV 0x80000000 /* map register valid */ | |
90 | #define UBA_BO 0x02000000 /* byte offset bit */ | |
91 | #define UBA_DPDB 0x01e00000 /* data path designator field */ | |
92 | #define UBA_SBIPFN 0x000fffff /* SBI page address field */ | |
93 | ||
94 | #define UBA_DPSHIFT 21 /* shift to data path designator */ | |
95 | ||
b5fa1937 | 96 | #ifndef LOCORE |
10a50234 | 97 | /* |
ca89a8ee BJ |
98 | * Each UNIBUS mass storage controller has uba_minfo structure, |
99 | * and a uba_dinfo structure (as below) for each attached drive. | |
10a50234 | 100 | */ |
15b39647 | 101 | struct uba_minfo { |
ca89a8ee BJ |
102 | struct uba_driver *um_driver; |
103 | short um_ctlr; /* controller index in driver */ | |
10a50234 BJ |
104 | short um_ubanum; /* the uba it is on */ |
105 | short um_alive; /* controller exists */ | |
ca89a8ee | 106 | int (**um_intr)(); /* interrupt handler(s) */ |
10a50234 | 107 | caddr_t um_addr; /* address of device in i/o space */ |
ca89a8ee | 108 | struct uba_hd *um_hd; |
15b39647 BJ |
109 | int um_cmd; /* communication to dgo() */ |
110 | int um_ubinfo; /* save unibus registers, etc */ | |
ca89a8ee | 111 | struct buf um_tab; /* queue for this controller */ |
1cb3d36a | 112 | }; |
10a50234 | 113 | /* |
ca89a8ee BJ |
114 | * Each UNIBUS device has a uba_dinfo structure. |
115 | * If a controller has many drives attached, then there will | |
116 | * be several uba_dinfo structures associated with a single uba_minfo | |
10a50234 BJ |
117 | * structure. |
118 | */ | |
15b39647 | 119 | struct uba_dinfo { |
10a50234 | 120 | struct uba_driver *ui_driver; |
10a50234 | 121 | short ui_unit; /* unit number on the system */ |
ca89a8ee | 122 | short ui_ctlr; /* mass ctlr number; -1 if none */ |
10a50234 BJ |
123 | short ui_ubanum; /* the uba it is on */ |
124 | short ui_slave; /* slave on controller */ | |
125 | int (**ui_intr)(); /* interrupt handler(s) */ | |
126 | caddr_t ui_addr; /* address of device in i/o space */ | |
15b39647 BJ |
127 | short ui_dk; /* if init 1 set to number for iostat */ |
128 | short ui_flags; /* param to device init. */ | |
10a50234 BJ |
129 | short ui_alive; /* device exists */ |
130 | short ui_type; /* driver specific type information */ | |
10a50234 | 131 | caddr_t ui_physaddr; /* phys addr, for standalone (dump) code */ |
15b39647 | 132 | struct uba_dinfo *ui_forw; |
bbe0bf68 | 133 | /* if the device isn't also a controller, this is the controller it is on */ |
10a50234 BJ |
134 | struct uba_minfo *ui_mi; |
135 | struct uba_hd *ui_hd; | |
136 | }; | |
b5fa1937 | 137 | #endif |
10a50234 BJ |
138 | |
139 | #define NUBA780 4 | |
140 | #define NUBA750 1 | |
141 | #if VAX780 | |
142 | #define MAXNUBA 4 | |
143 | #else | |
144 | #define MAXNUBA 1 | |
145 | #endif | |
466a1b4c | 146 | |
b5fa1937 | 147 | #ifndef LOCORE |
10a50234 | 148 | /* |
ca89a8ee | 149 | * This structure exists per-uba. |
10a50234 BJ |
150 | */ |
151 | struct uba_hd { | |
10a50234 BJ |
152 | struct uba_regs *uh_uba; /* virt addr of uba */ |
153 | struct uba_regs *uh_physuba; /* phys addr of uba */ | |
154 | int (**uh_vec)(); /* interrupt vector */ | |
15b39647 BJ |
155 | struct uba_dinfo *uh_actf; /* head of queue to transfer */ |
156 | struct uba_dinfo *uh_actl; /* tail of queue to transfer */ | |
10a50234 BJ |
157 | short uh_mrwant; /* someone is waiting for map reg */ |
158 | short uh_bdpwant; /* someone awaits bdp's */ | |
159 | int uh_bdpfree; /* free bdp's */ | |
160 | int uh_hangcnt; /* number of ticks hung */ | |
161 | int uh_zvcnt; /* number of 0 vectors */ | |
7e51b323 BJ |
162 | short uh_users; /* transient bdp use count */ |
163 | short uh_xclu; /* an rk07 is using this uba! */ | |
ca89a8ee BJ |
164 | #define UAMSIZ 50 |
165 | struct map *uh_map; | |
b5fa1937 BJ |
166 | }; |
167 | #ifdef KERNEL | |
168 | struct uba_hd uba_hd[MAXNUBA]; | |
169 | #endif | |
10a50234 | 170 | /* |
ca89a8ee | 171 | * Each UNIBUS driver defines entries for a set of routines |
10a50234 BJ |
172 | * as well as an array of types which are acceptable to it. |
173 | */ | |
174 | struct uba_driver { | |
bbe0bf68 BJ |
175 | int (*ud_probe)(); /* see if a driver is really there */ |
176 | int (*ud_slave)(); /* see if a slave is there */ | |
177 | int (*ud_attach)(); /* setup driver for a slave */ | |
178 | int (*ud_dgo)(); /* fill csr/ba to start transfer */ | |
10a50234 | 179 | u_short *ud_addr; /* device csr addresses */ |
15b39647 | 180 | char *ud_dname; /* name of a device */ |
ca89a8ee | 181 | struct uba_dinfo **ud_dinfo; /* backpointers to ubdinit structs */ |
15b39647 | 182 | char *ud_mname; /* name of a controller */ |
ca89a8ee | 183 | struct uba_minfo **ud_minfo; /* backpointers to ubminit structs */ |
8786ef2e | 184 | short ud_xclu; /* want exclusive use of bdp's */ |
466a1b4c | 185 | }; |
b5fa1937 | 186 | #endif |
466a1b4c | 187 | |
10a50234 BJ |
188 | /* |
189 | * unibus maps | |
190 | */ | |
191 | #define NBDP780 15 | |
192 | #define NBDP750 3 | |
193 | #define MAXNBDP 15 | |
194 | ||
195 | #define NUBMREG 496 | |
196 | ||
197 | /* | |
198 | * flags to uba map/bdp allocation routines | |
199 | */ | |
200 | #define UBA_NEEDBDP 1 /* transfer needs a bdp */ | |
201 | #define UBA_CANTWAIT 2 /* don't block me */ | |
202 | #define UBA_NEED16 3 /* need 16 bit addresses only */ | |
15b39647 BJ |
203 | |
204 | /* | |
205 | * UNIBUS related kernel variables | |
206 | */ | |
b5fa1937 | 207 | #ifndef LOCORE |
15b39647 BJ |
208 | #ifdef KERNEL |
209 | extern struct uba_minfo ubminit[]; | |
210 | extern struct uba_dinfo ubdinit[]; | |
211 | int numuba; | |
212 | extern struct pte UMEMmap[MAXNUBA][16]; | |
213 | extern char umem[MAXNUBA][16*NBPG]; | |
214 | extern int (*UNIvec[])(); | |
215 | #if VAX780 | |
216 | extern Xua0int(), Xua1int(), Xua2int(), Xua3int(); | |
217 | #endif | |
218 | #endif | |
b5fa1937 | 219 | #endif |