/* Subroutines used by or related to instruction recognition.
Copyright (C) 1987, 1988, 1991, 1992, 1993 Free Software Foundation, Inc.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#include "hard-reg-set.h"
#ifdef STACK_GROWS_DOWNWARD
#define STACK_PUSH_CODE PRE_DEC
#define STACK_PUSH_CODE PRE_INC
/* Import from final.c: */
extern rtx
alter_subreg ();
int strict_memory_address_p ();
/* Nonzero means allow operands to be volatile.
This should be 0 if you are generating rtl, such as if you are calling
the functions in optabs.c and expmed.c (most of the time).
This should be 1 if all valid insns need to be recognized,
such as in regclass.c and final.c and reload.c.
init_recog and init_recog_no_volatile are responsible for setting this. */
/* On return from `constrain_operands', indicate which alternative
/* Nonzero after end of reload pass.
Set to 1 or 0 by toplev.c.
Controls the significance of (SUBREG (MEM)). */
/* Initialize data used by the function `recog'.
This must be called once in the compilation of a function
before any insn recognition may be done in the function. */
init_recog_no_volatile ()
/* Try recognizing the instruction INSN,
and return the code number that results.
Remeber the code so that repeated calls do not
need to spend the time for actual rerecognition.
This function is the normal interface to instruction recognition.
The automatically-generated function `recog' is normally called
through this one. (The only exception is in combine.c.) */
if (INSN_CODE (insn
) < 0)
INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, NULL_PTR
);
/* Check that X is an insn-body for an `asm' with operands
and that the operands mentioned in it are legitimate. */
int noperands
= asm_noperands (x
);
operands
= (rtx
*) alloca (noperands
* sizeof (rtx
));
decode_asm_operands (x
, operands
, NULL_PTR
, NULL_PTR
, NULL_PTR
);
for (i
= 0; i
< noperands
; i
++)
if (!general_operand (operands
[i
], VOIDmode
))
/* Static data for the next two routines.
The maximum number of changes supported is defined as the maximum
number of operands times 5. This allows for repeated substitutions
inside complex indexed address, or, alternatively, changes in up
#define MAX_CHANGE_LOCS (MAX_RECOG_OPERANDS * 5)
static rtx change_objects
[MAX_CHANGE_LOCS
];
static int change_old_codes
[MAX_CHANGE_LOCS
];
static rtx
*change_locs
[MAX_CHANGE_LOCS
];
static rtx change_olds
[MAX_CHANGE_LOCS
];
static int num_changes
= 0;
/* Validate a proposed change to OBJECT. LOC is the location in the rtl for
at which NEW will be placed. If OBJECT is zero, no validation is done,
the change is simply made.
Two types of objects are supported: If OBJECT is a MEM, memory_address_p
will be called with the address and mode as parameters. If OBJECT is
an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
IN_GROUP is non-zero if this is part of a group of changes that must be
performed as a group. In that case, the changes will be stored. The
function `apply_change_group' will validate and apply the changes.
If IN_GROUP is zero, this is a single change. Try to recognize the insn
or validate the memory reference with the change applied. If the result
is not valid for the machine, suppress the change and return zero.
Otherwise, perform the change and return 1. */
validate_change (object
, loc
, new, in_group
)
if (old
== new || rtx_equal_p (old
, new))
if (num_changes
>= MAX_CHANGE_LOCS
|| (in_group
== 0 && num_changes
!= 0))
/* Save the information describing this change. */
change_objects
[num_changes
] = object
;
change_locs
[num_changes
] = loc
;
change_olds
[num_changes
] = old
;
if (object
&& GET_CODE (object
) != MEM
)
/* Set INSN_CODE to force rerecognition of insn. Save old code in
change_old_codes
[num_changes
] = INSN_CODE (object
);
/* If we are making a group of changes, return 1. Otherwise, validate the
return apply_change_group ();
/* Apply a group of changes previously issued with `validate_change'.
Return 1 if all changes are valid, zero otherwise. */
/* The changes have been applied and all INSN_CODEs have been reset to force
The changes are valid if we aren't given an object, or if we are
given a MEM and it still is a valid address, or if this is in insn
and it is recognized. In the latter case, if reload has completed,
we also require that the operands meet the constraints for
the insn. We do not allow modifying an ASM_OPERANDS after reload
has completed because verifying the constraints is too difficult. */
for (i
= 0; i
< num_changes
; i
++)
rtx object
= change_objects
[i
];
if (GET_CODE (object
) == MEM
)
if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
else if ((recog_memoized (object
) < 0
&& (asm_noperands (PATTERN (object
)) < 0
|| ! check_asm_operands (PATTERN (object
))
&& (insn_extract (object
),
! constrain_operands (INSN_CODE (object
), 1))))
rtx pat
= PATTERN (object
);
/* Perhaps we couldn't recognize the insn because there were
extra CLOBBERs at the end. If so, try to re-recognize
without the last CLOBBER (later iterations will cause each of
them to be eliminated, in turn). But don't do this if we
if (GET_CODE (pat
) == PARALLEL
&& GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
&& asm_noperands (PATTERN (object
)) < 0)
if (XVECLEN (pat
, 0) == 2)
newpat
= XVECEXP (pat
, 0, 0);
newpat
= gen_rtx (PARALLEL
, VOIDmode
,
gen_rtvec (XVECLEN (pat
, 0) - 1));
for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
/* Add a new change to this group to replace the pattern
with this new pattern. Then consider this change
as having succeeded. The change we added will
cause the entire call to fail if things remain invalid.
Note that this can lose if a later change than the one
we are processing specified &XVECEXP (PATTERN (object), 0, X)
but this shouldn't occur. */
validate_change (object
, &PATTERN (object
), newpat
, 1);
else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
/* If this insn is a CLOBBER or USE, it is always valid, but is
/* Return the number of changes so far in the current group. */
/* Retract the changes numbered NUM and up. */
/* Back out all the changes. Do this in the opposite order in which
for (i
= num_changes
- 1; i
>= num
; i
--)
*change_locs
[i
] = change_olds
[i
];
if (change_objects
[i
] && GET_CODE (change_objects
[i
]) != MEM
)
INSN_CODE (change_objects
[i
]) = change_old_codes
[i
];
/* Replace every occurrence of FROM in X with TO. Mark each change with
validate_change passing OBJECT. */
validate_replace_rtx_1 (loc
, from
, to
, object
)
enum rtx_code code
= GET_CODE (x
);
/* X matches FROM if it is the same rtx or they are both referring to the
same register in the same mode. Avoid calling rtx_equal_p unless the
operands look similar. */
|| (GET_CODE (x
) == REG
&& GET_CODE (from
) == REG
&& GET_MODE (x
) == GET_MODE (from
)
&& REGNO (x
) == REGNO (from
))
|| (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
&& rtx_equal_p (x
, from
)))
validate_change (object
, loc
, to
, 1);
/* For commutative or comparison operations, try replacing each argument
separately and seeing if we made any changes. If so, put a constant
if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
int prev_changes
= num_changes
;
validate_replace_rtx_1 (&XEXP (x
, 0), from
, to
, object
);
validate_replace_rtx_1 (&XEXP (x
, 1), from
, to
, object
);
if (prev_changes
!= num_changes
&& CONSTANT_P (XEXP (x
, 0)))
validate_change (object
, loc
,
gen_rtx (GET_RTX_CLASS (code
) == 'c' ? code
GET_MODE (x
), XEXP (x
, 1), XEXP (x
, 0)),
/* If we have have a PLUS whose second operand is now a CONST_INT, use
plus_constant to try to simplify it. */
if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& XEXP (x
, 1) == to
)
validate_change (object
, loc
,
plus_constant (XEXP (x
, 0), INTVAL (XEXP (x
, 1))), 1);
/* In these cases, the operation to be performed depends on the mode
of the operand. If we are replacing the operand with a VOIDmode
constant, we lose the information. So try to simplify the operation
in that case. If it fails, substitute in something that we know
if (GET_MODE (to
) == VOIDmode
|| (GET_CODE (XEXP (x
, 0)) == REG
&& GET_CODE (from
) == REG
&& GET_MODE (XEXP (x
, 0)) == GET_MODE (from
)
&& REGNO (XEXP (x
, 0)) == REGNO (from
))))
rtx
new = simplify_unary_operation (code
, GET_MODE (x
), to
,
new = gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
validate_change (object
, loc
, new, 1);
/* If we have a SUBREG of a register that we are replacing and we are
replacing it with a MEM, make a new MEM and try replacing the
SUBREG with it. Don't do this if the MEM has a mode-dependent address
or if we would be widening it. */
if (SUBREG_REG (x
) == from
&& GET_CODE (from
) == REG
&& ! mode_dependent_address_p (XEXP (to
, 0))
&& GET_MODE_SIZE (GET_MODE (x
)) <= GET_MODE_SIZE (GET_MODE (to
)))
int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
enum machine_mode mode
= GET_MODE (x
);
offset
+= (MIN (UNITS_PER_WORD
,
GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
- MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
new = gen_rtx (MEM
, mode
, plus_constant (XEXP (to
, 0), offset
));
MEM_VOLATILE_P (new) = MEM_VOLATILE_P (to
);
RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to
);
MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (to
);
validate_change (object
, loc
, new, 1);
/* If we are replacing a register with memory, try to change the memory
to be the mode required for memory in extract operations (this isn't
likely to be an insertion operation; if it was, nothing bad will
happen, we might just fail in some cases). */
if (XEXP (x
, 0) == from
&& GET_CODE (from
) == REG
&& GET_CODE (to
) == MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
&& GET_CODE (XEXP (x
, 2)) == CONST_INT
&& ! mode_dependent_address_p (XEXP (to
, 0))
&& ! MEM_VOLATILE_P (to
))
enum machine_mode wanted_mode
= VOIDmode
;
enum machine_mode is_mode
= GET_MODE (to
);
int width
= INTVAL (XEXP (x
, 1));
int pos
= INTVAL (XEXP (x
, 2));
if (code
== ZERO_EXTRACT
)
wanted_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][1];
if (code
== SIGN_EXTRACT
)
wanted_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][1];
/* If we have a narrower mode, we can do something. */
if (wanted_mode
!= VOIDmode
&& GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
int offset
= pos
/ BITS_PER_UNIT
;
/* If the bytes and bits are counted differently, we
must adjust the offset. */
#if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
offset
= (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
)
pos
%= GET_MODE_BITSIZE (wanted_mode
);
newmem
= gen_rtx (MEM
, wanted_mode
,
plus_constant (XEXP (to
, 0), offset
));
RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (to
);
MEM_VOLATILE_P (newmem
) = MEM_VOLATILE_P (to
);
MEM_IN_STRUCT_P (newmem
) = MEM_IN_STRUCT_P (to
);
validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
validate_change (object
, &XEXP (x
, 0), newmem
, 1);
fmt
= GET_RTX_FORMAT (code
);
for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
/* Try replacing every occurrence of FROM in INSN with TO. After all
changes have been made, validate by seeing if INSN is still valid. */
validate_replace_rtx (from
, to
, insn
)
validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
return apply_change_group ();
/* Return 1 if the insn using CC0 set by INSN does not contain
any ordered tests applied to the condition codes.
EQ and NE tests do not count. */
next_insn_tests_no_inequality (insn
)
register rtx next
= next_cc0_user (insn
);
/* If there is no next insn, we have to take the conservative choice. */
return ((GET_CODE (next
) == JUMP_INSN
|| GET_CODE (next
) == INSN
|| GET_CODE (next
) == CALL_INSN
)
&& ! inequality_comparisons_p (PATTERN (next
)));
#if 0 /* This is useless since the insn that sets the cc's
must be followed immediately by the use of them. */
/* Return 1 if the CC value set up by INSN is not used. */
next_insns_test_no_inequality (insn
)
register rtx next
= NEXT_INSN (insn
);
for (; next
!= 0; next
= NEXT_INSN (next
))
if (GET_CODE (next
) == CODE_LABEL
|| GET_CODE (next
) == BARRIER
)
if (GET_CODE (next
) == NOTE
)
if (inequality_comparisons_p (PATTERN (next
)))
if (sets_cc0_p (PATTERN (next
)) == 1)
if (! reg_mentioned_p (cc0_rtx
, PATTERN (next
)))
/* This is used by find_single_use to locate an rtx that contains exactly one
use of DEST, which is typically either a REG or CC0. It returns a
pointer to the innermost rtx expression containing DEST. Appearances of
DEST that are being used to totally replace it are not counted. */
find_single_use_1 (dest
, loc
)
enum rtx_code code
= GET_CODE (x
);
/* If the destination is anything other than CC0, PC, a REG or a SUBREG
of a REG that occupies all of the REG, the insn uses DEST if
it is mentioned in the destination or the source. Otherwise, we
need just check the source. */
if (GET_CODE (SET_DEST (x
)) != CC0
&& GET_CODE (SET_DEST (x
)) != PC
&& GET_CODE (SET_DEST (x
)) != REG
&& ! (GET_CODE (SET_DEST (x
)) == SUBREG
&& GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
&& (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
+ (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
== ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
+ (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
return find_single_use_1 (dest
, &SET_SRC (x
));
return find_single_use_1 (dest
, &XEXP (x
, 0));
/* If it wasn't one of the common cases above, check each expression and
vector of this code. Look for a unique usage of DEST. */
fmt
= GET_RTX_FORMAT (code
);
for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
|| (GET_CODE (dest
) == REG
&& GET_CODE (XEXP (x
, i
)) == REG
&& REGNO (dest
) == REGNO (XEXP (x
, i
))))
this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
if (XVECEXP (x
, i
, j
) == dest
|| (GET_CODE (dest
) == REG
&& GET_CODE (XVECEXP (x
, i
, j
)) == REG
&& REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
/* See if DEST, produced in INSN, is used only a single time in the
sequel. If so, return a pointer to the innermost rtx expression in which
If PLOC is non-zero, *PLOC is set to the insn containing the single use.
This routine will return usually zero either before flow is called (because
there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
care about REG_DEAD notes or LOG_LINKS.
Otherwise, we find the single use by finding an insn that has a
LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
only referenced once in that insn, we know that it must be the first
and last insn referencing DEST. */
find_single_use (dest
, insn
, ploc
)
|| (GET_CODE (next
) != INSN
&& GET_CODE (next
) != JUMP_INSN
))
result
= find_single_use_1 (dest
, &PATTERN (next
));
if (reload_completed
|| reload_in_progress
|| GET_CODE (dest
) != REG
)
for (next
= next_nonnote_insn (insn
);
next
!= 0 && GET_CODE (next
) != CODE_LABEL
;
next
= next_nonnote_insn (next
))
if (GET_RTX_CLASS (GET_CODE (next
)) == 'i' && dead_or_set_p (next
, dest
))
for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
if (XEXP (link
, 0) == insn
)
result
= find_single_use_1 (dest
, &PATTERN (next
));
/* Return 1 if OP is a valid general operand for machine mode MODE.
This is either a register reference, a memory reference,
or a constant. In the case of a memory reference, the address
is checked for general validity for the target machine.
Register and memory references must have mode MODE in order to be valid,
but some constants have no machine mode and are valid for any mode.
If MODE is VOIDmode, OP is checked for validity for whatever mode
The main use of this function is as a predicate in match_operand
expressions in the machine description.
For an explanation of this function's behavior for registers of
class NO_REGS, see the comment for `register_operand'. */
general_operand (op
, mode
)
register enum rtx_code code
= GET_CODE (op
);
int mode_altering_drug
= 0;
/* Don't accept CONST_INT or anything similar
if the caller wants something floating. */
if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) != MODE_INT
&& GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
)
#ifdef LEGITIMATE_PIC_OPERAND_P
&& (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
&& LEGITIMATE_CONSTANT_P (op
));
/* Except for certain constants with VOIDmode, already checked for,
OP's mode must match MODE if MODE specifies a mode. */
if (GET_MODE (op
) != mode
)
/* On machines that have insn scheduling, we want all memory
reference to be explicit, so outlaw paradoxical SUBREGs. */
if (GET_CODE (SUBREG_REG (op
)) == MEM
&& GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
/* No longer needed, since (SUBREG (MEM...))
will load the MEM into a reload reg in the MEM's own mode. */
/* A register whose class is NO_REGS is not a general operand. */
return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
register rtx y
= XEXP (op
, 0);
if (! volatile_ok
&& MEM_VOLATILE_P (op
))
/* Use the mem's mode, since it will be reloaded thus. */
GO_IF_LEGITIMATE_ADDRESS (mode
, y
, win
);
return ! mode_dependent_address_p (XEXP (op
, 0));
/* Return 1 if OP is a valid memory address for a memory reference
The main use of this function is as a predicate in match_operand
expressions in the machine description. */
address_operand (op
, mode
)
return memory_address_p (mode
, op
);
/* Return 1 if OP is a register reference of mode MODE.
If MODE is VOIDmode, accept a register in any mode.
The main use of this function is as a predicate in match_operand
expressions in the machine description.
As a special exception, registers whose class is NO_REGS are
not accepted by `register_operand'. The reason for this change
is to allow the representation of special architecture artifacts
(such as a condition code register) without extending the rtl
definitions. Since registers of class NO_REGS cannot be used
as registers in any case where register classes are examined,
it is most consistent to keep this function from accepting them. */
register_operand (op
, mode
)
if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
if (GET_CODE (op
) == SUBREG
)
/* Before reload, we can allow (SUBREG (MEM...)) as a register operand
because it is guaranteed to be reloaded into one.
Just make sure the MEM is valid in itself.
(Ideally, (SUBREG (MEM)...) should not exist after reload,
but currently it does result from (SUBREG (REG)...) where the
reg went on the stack.) */
if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
return general_operand (op
, mode
);
/* We don't consider registers whose class is NO_REGS
to be a register operand. */
return (GET_CODE (op
) == REG
&& (REGNO (op
) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
/* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
scratch_operand (op
, mode
)
return (GET_MODE (op
) == mode
&& (GET_CODE (op
) == SCRATCH
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)));
/* Return 1 if OP is a valid immediate operand for mode MODE.
The main use of this function is as a predicate in match_operand
expressions in the machine description. */
immediate_operand (op
, mode
)
/* Don't accept CONST_INT or anything similar
if the caller wants something floating. */
if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) != MODE_INT
&& GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
&& (GET_MODE (op
) == mode
|| mode
== VOIDmode
|| GET_MODE (op
) == VOIDmode
)
#ifdef LEGITIMATE_PIC_OPERAND_P
&& (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
&& LEGITIMATE_CONSTANT_P (op
));
/* Returns 1 if OP is an operand that is a CONST_INT. */
const_int_operand (op
, mode
)
return GET_CODE (op
) == CONST_INT
;
/* Returns 1 if OP is an operand that is a constant integer or constant
floating-point number. */
const_double_operand (op
, mode
)
/* Don't accept CONST_INT or anything similar
if the caller wants something floating. */
if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) != MODE_INT
&& GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
&& (mode
== VOIDmode
|| GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
));
/* Return 1 if OP is a general operand that is not an immediate operand. */
nonimmediate_operand (op
, mode
)
return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
/* Return 1 if OP is a register reference or immediate value of mode MODE. */
nonmemory_operand (op
, mode
)
/* Don't accept CONST_INT or anything similar
if the caller wants something floating. */
if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) != MODE_INT
&& GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
)
#ifdef LEGITIMATE_PIC_OPERAND_P
&& (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
&& LEGITIMATE_CONSTANT_P (op
));
if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
if (GET_CODE (op
) == SUBREG
)
/* Before reload, we can allow (SUBREG (MEM...)) as a register operand
because it is guaranteed to be reloaded into one.
Just make sure the MEM is valid in itself.
(Ideally, (SUBREG (MEM)...) should not exist after reload,
but currently it does result from (SUBREG (REG)...) where the
reg went on the stack.) */
if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
return general_operand (op
, mode
);
/* We don't consider registers whose class is NO_REGS
to be a register operand. */
return (GET_CODE (op
) == REG
&& (REGNO (op
) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
/* Return 1 if OP is a valid operand that stands for pushing a
value of mode MODE onto the stack.
The main use of this function is as a predicate in match_operand
expressions in the machine description. */
if (GET_CODE (op
) != MEM
)
if (GET_MODE (op
) != mode
)
if (GET_CODE (op
) != STACK_PUSH_CODE
)
return XEXP (op
, 0) == stack_pointer_rtx
;
/* Return 1 if ADDR is a valid memory address for mode MODE. */
memory_address_p (mode
, addr
)
GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
/* Return 1 if OP is a valid memory reference with mode MODE,
including a valid address.
The main use of this function is as a predicate in match_operand
expressions in the machine description. */
memory_operand (op
, mode
)
/* Note that no SUBREG is a memory operand before end of reload pass,
because (SUBREG (MEM...)) forces reloading into a register. */
return GET_CODE (op
) == MEM
&& general_operand (op
, mode
);
if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
if (GET_CODE (inner
) == SUBREG
)
inner
= SUBREG_REG (inner
);
return (GET_CODE (inner
) == MEM
&& general_operand (op
, mode
));
/* Return 1 if OP is a valid indirect memory reference with mode MODE;
that is, a memory reference whose address is a general_operand. */
indirect_operand (op
, mode
)
/* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
&& GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
register int offset
= SUBREG_WORD (op
) * UNITS_PER_WORD
;
rtx inner
= SUBREG_REG (op
);
offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (op
)))
- MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (inner
))));
/* The only way that we can have a general_operand as the resulting
address is if OFFSET is zero and the address already is an operand
or if the address is (plus Y (const_int -OFFSET)) and Y is an
return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
|| (GET_CODE (XEXP (inner
, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
&& INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
&& general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
return (GET_CODE (op
) == MEM
&& memory_operand (op
, mode
)
&& general_operand (XEXP (op
, 0), Pmode
));
/* Return 1 if this is a comparison operator. This allows the use of
MATCH_OPERATOR to recognize all the branch insns. */
comparison_operator (op
, mode
)
return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
&& GET_RTX_CLASS (GET_CODE (op
)) == '<');
/* If BODY is an insn body that uses ASM_OPERANDS,
return the number of operands (both input and output) in the insn.
if (GET_CODE (body
) == ASM_OPERANDS
)
/* No output operands: return number of input operands. */
return ASM_OPERANDS_INPUT_LENGTH (body
);
if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
/* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
else if (GET_CODE (body
) == PARALLEL
&& GET_CODE (XVECEXP (body
, 0, 0)) == SET
&& GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
/* Multiple output operands, or 1 output plus some clobbers:
body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
/* Count backwards through CLOBBERs to determine number of SETs. */
for (i
= XVECLEN (body
, 0); i
> 0; i
--)
if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
/* N_SETS is now number of output operands. */
/* Verify that all the SETs we have
came from a single original asm_operands insn
(so that invalid combinations are blocked). */
for (i
= 0; i
< n_sets
; i
++)
rtx elt
= XVECEXP (body
, 0, i
);
if (GET_CODE (elt
) != SET
)
if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
/* If these ASM_OPERANDS rtx's came from different original insns
then they aren't allowed together. */
if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
!= ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
else if (GET_CODE (body
) == PARALLEL
&& GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
/* 0 outputs, but some clobbers:
body is [(asm_operands ...) (clobber (reg ...))...]. */
/* Make sure all the other parallel things really are clobbers. */
for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
/* Assuming BODY is an insn body that uses ASM_OPERANDS,
copy its operands (both input and output) into the vector OPERANDS,
the locations of the operands within the insn into the vector OPERAND_LOCS,
and the constraints for the operands into CONSTRAINTS.
Write the modes of the operands into MODES.
Return the assembler-template.
If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
we don't store that info. */
decode_asm_operands (body
, operands
, operand_locs
, constraints
, modes
)
enum machine_mode
*modes
;
if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
rtx asmop
= SET_SRC (body
);
/* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
for (i
= 1; i
< noperands
; i
++)
operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
/* The output is in the SET.
Its constraint is in the ASM_OPERANDS itself. */
operands
[0] = SET_DEST (body
);
operand_locs
[0] = &SET_DEST (body
);
constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
modes
[0] = GET_MODE (SET_DEST (body
));
template = ASM_OPERANDS_TEMPLATE (asmop
);
else if (GET_CODE (body
) == ASM_OPERANDS
)
/* No output operands: BODY is (asm_operands ....). */
noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
/* The input operands are found in the 1st element vector. */
/* Constraints for inputs are in the 2nd element vector. */
for (i
= 0; i
< noperands
; i
++)
operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
template = ASM_OPERANDS_TEMPLATE (asmop
);
else if (GET_CODE (body
) == PARALLEL
&& GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
int nout
= 0; /* Does not include CLOBBERs. */
/* At least one output, plus some CLOBBERs. */
/* The outputs are in the SETs.
Their constraints are in the ASM_OPERANDS itself. */
for (i
= 0; i
< nparallel
; i
++)
if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
break; /* Past last SET */
operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
for (i
= 0; i
< nin
; i
++)
operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
template = ASM_OPERANDS_TEMPLATE (asmop
);
else if (GET_CODE (body
) == PARALLEL
&& GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
/* No outputs, but some CLOBBERs. */
rtx asmop
= XVECEXP (body
, 0, 0);
int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
for (i
= 0; i
< nin
; i
++)
operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
template = ASM_OPERANDS_TEMPLATE (asmop
);
/* Given an rtx *P, if it is a sum containing an integer constant term,
return the location (type rtx *) of the pointer to that constant term.
Otherwise, return a null pointer. */
find_constant_term_loc (p
)
register enum rtx_code code
= GET_CODE (*p
);
/* If *P IS such a constant term, P is its location. */
if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
/* Otherwise, if not a sum, it has no constant term. */
if (GET_CODE (*p
) != PLUS
)
/* If one of the summands is constant, return its location. */
if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
&& XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
/* Otherwise, check each summand for containing a constant term. */
tem
= find_constant_term_loc (&XEXP (*p
, 0));
tem
= find_constant_term_loc (&XEXP (*p
, 1));
/* Return 1 if OP is a memory reference
whose address contains no side effects
and remains valid after the addition
of a positive integer less than the
size of the object being referenced.
We assume that the original address is valid and do not check it.
This uses strict_memory_address_p as a subroutine, so
don't use it before reload. */
offsettable_memref_p (op
)
return ((GET_CODE (op
) == MEM
)
&& offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
/* Similar, but don't require a strictly valid mem ref:
consider pseudo-regs valid as index or base regs. */
offsettable_nonstrict_memref_p (op
)
return ((GET_CODE (op
) == MEM
)
&& offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
/* Return 1 if Y is a memory address which contains no side effects
and would remain valid after the addition of a positive integer
less than the size of that mode.
We assume that the original address is valid and do not check it.
We do check that it is valid for narrower modes.
If STRICTP is nonzero, we require a strictly valid address,
for the sake of use in reload.c. */
offsettable_address_p (strictp
, mode
, y
)
register enum rtx_code ycode
= GET_CODE (y
);
int (*addressp
) () = (strictp
? strict_memory_address_p
: memory_address_p
);
if (CONSTANT_ADDRESS_P (y
))
/* Adjusting an offsettable address involves changing to a narrower mode.
if (mode_dependent_address_p (y
))
/* If the expression contains a constant term,
see if it remains valid when max possible offset is added. */
if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
*y2
= plus_constant (*y2
, GET_MODE_SIZE (mode
) - 1);
/* Use QImode because an odd displacement may be automatically invalid
for any wider mode. But it should be valid for a single byte. */
good
= (*addressp
) (QImode
, y
);
/* In any case, restore old contents of memory. */
if (ycode
== PRE_DEC
|| ycode
== PRE_INC
|| ycode
== POST_DEC
|| ycode
== POST_INC
)
/* The offset added here is chosen as the maximum offset that
any instruction could need to add when operating on something
of the specified mode. We assume that if Y and Y+c are
valid addresses then so is Y+d for all 0<d<c. */
z
= plus_constant_for_output (y
, GET_MODE_SIZE (mode
) - 1);
/* Use QImode because an odd displacement may be automatically invalid
for any wider mode. But it should be valid for a single byte. */
return (*addressp
) (QImode
, z
);
/* Return 1 if ADDR is an address-expression whose effect depends
on the mode of the memory reference it is used in.
Autoincrement addressing is a typical example of mode-dependence
because the amount of the increment depends on the mode. */
mode_dependent_address_p (addr
)
GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
/* Return 1 if OP is a general operand
other than a memory ref with a mode dependent address. */
mode_independent_operand (op
, mode
)
if (! general_operand (op
, mode
))
if (GET_CODE (op
) != MEM
)
GO_IF_MODE_DEPENDENT_ADDRESS (addr
, lose
);
/* Given an operand OP that is a valid memory reference
which satisfies offsettable_memref_p,
return a new memory reference whose address has been adjusted by OFFSET.
OFFSET should be positive and less than the size of the object referenced.
adj_offsettable_operand (op
, offset
)
register enum rtx_code code
= GET_CODE (op
);
register rtx y
= XEXP (op
, 0);
if (CONSTANT_ADDRESS_P (y
))
new = gen_rtx (MEM
, GET_MODE (op
), plus_constant_for_output (y
, offset
));
RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op
);
if (GET_CODE (y
) == PLUS
)
const_loc
= find_constant_term_loc (&z
);
*const_loc
= plus_constant_for_output (*const_loc
, offset
);
new = gen_rtx (MEM
, GET_MODE (op
), plus_constant_for_output (y
, offset
));
RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op
);
#ifdef REGISTER_CONSTRAINTS
/* Check the operands of an insn (found in recog_operands)
against the insn's operand constraints (found via INSN_CODE_NUM)
and return 1 if they are valid.
WHICH_ALTERNATIVE is set to a number which indicates which
alternative of constraints was matched: 0 for the first alternative,
In addition, when two operands are match
and it happens that the output operand is (reg) while the
input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
make the output operand look like the input.
This is because the output operand is the one the template will print.
This is used in final, just before printing the assembler code and by
the routines that determine an insn's attribute.
If STRICT is a positive non-zero value, it means that we have been
called after reload has been completed. In that case, we must
do all checks strictly. If it is zero, it means that we have been called
before reload has completed. In that case, we first try to see if we can
find an alternative that matches strictly. If not, we try again, this
time assuming that reload will fix up the insn. This provides a "best
guess" for the alternative and is used to compute attributes of insns prior
to reload. A negative value of STRICT is used for this internal call. */
constrain_operands (insn_code_num
, strict
)
char *constraints
[MAX_RECOG_OPERANDS
];
int matching_operands
[MAX_RECOG_OPERANDS
];
enum op_type
{OP_IN
, OP_OUT
, OP_INOUT
} op_types
[MAX_RECOG_OPERANDS
];
int earlyclobber
[MAX_RECOG_OPERANDS
];
int noperands
= insn_n_operands
[insn_code_num
];
struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
int nalternatives
= insn_n_alternatives
[insn_code_num
];
if (noperands
== 0 || nalternatives
== 0)
for (c
= 0; c
< noperands
; c
++)
constraints
[c
] = insn_operand_constraint
[insn_code_num
][c
];
matching_operands
[c
] = -1;
while (which_alternative
< nalternatives
)
for (opno
= 0; opno
< noperands
; opno
++)
register rtx op
= recog_operand
[opno
];
enum machine_mode mode
= GET_MODE (op
);
register char *p
= constraints
[opno
];
if (GET_CODE (op
) == SUBREG
)
if (GET_CODE (SUBREG_REG (op
)) == REG
&& REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
offset
= SUBREG_WORD (op
);
/* An empty constraint or empty alternative
allows anything which matched the pattern. */
if (*p
== 0 || *p
== ',')
while (*p
&& (c
= *p
++) != ',')
op_types
[opno
] = OP_INOUT
;
/* This operand must be the same as a previous one.
This kind of constraint is used for instructions such
as add when they take only two operands.
Note that the lower-numbered operand is passed first.
If we are not testing strictly, assume that this constraint
val
= operands_match_p (recog_operand
[c
- '0'],
matching_operands
[opno
] = c
- '0';
matching_operands
[c
- '0'] = opno
;
/* If output is *x and input is *--x,
arrange later to change the output to *--x as well,
since the output op is the one that will be printed. */
if (val
== 2 && strict
> 0)
funny_match
[funny_match_index
].this = opno
;
funny_match
[funny_match_index
++].other
= c
- '0';
/* p is used for address_operands. When we are called by
gen_input_reload, no one will have checked that the
address is strictly valid, i.e., that all pseudos
requiring hard regs have gotten them. */
|| (strict_memory_address_p
(insn_operand_mode
[insn_code_num
][opno
], op
)))
/* No need to check general_operand again;
it was done in insn-recog.c. */
/* Anything goes unless it is a REG and really has a hard reg
but the hard reg is not in the class GENERAL_REGS. */
|| GENERAL_REGS
== ALL_REGS
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
|| reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
|| (strict
== 0 && GET_CODE (op
) == SCRATCH
)
&& ((GENERAL_REGS
== ALL_REGS
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)
|| reg_fits_class_p (op
, GENERAL_REGS
,
/* This is used for a MATCH_SCRATCH in the cases when we
don't actually need anything. So anything goes any time. */
/* Before reload, accept what reload can turn into mem. */
|| (strict
< 0 && CONSTANT_P (op
))
/* During reload, accept a pseudo */
|| (reload_in_progress
&& GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
&& (GET_CODE (XEXP (op
, 0)) == PRE_DEC
|| GET_CODE (XEXP (op
, 0)) == POST_DEC
))
&& (GET_CODE (XEXP (op
, 0)) == PRE_INC
|| GET_CODE (XEXP (op
, 0)) == POST_INC
))
/* Match any CONST_DOUBLE, but only if
we can examine the bits of it reliably. */
if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
|| HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
&& GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
if (GET_CODE (op
) == CONST_DOUBLE
)
if (GET_CODE (op
) == CONST_DOUBLE
)
if (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
if (GET_CODE (op
) == CONST_INT
|| (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
))
if (GET_CODE (op
) == CONST_INT
|| (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
))
if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
if (EXTRA_CONSTRAINT (op
, c
))
&& ! offsettable_memref_p (op
))
if ((strict
> 0 && offsettable_memref_p (op
))
|| (strict
== 0 && offsettable_nonstrict_memref_p (op
))
/* Before reload, accept what reload can handle. */
&& (CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
/* During reload, accept a pseudo */
|| (reload_in_progress
&& GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
|| (strict
== 0 && GET_CODE (op
) == SCRATCH
)
&& reg_fits_class_p (op
, REG_CLASS_FROM_LETTER (c
),
/* If this operand did not win somehow,
this alternative loses. */
/* This alternative won; the operands are ok.
Change whichever operands this alternative says to change. */
/* See if any earlyclobber operand conflicts with some other
for (eopno
= 0; eopno
< noperands
; eopno
++)
/* Ignore earlyclobber operands now in memory,
because we would often report failure when we have
two memory operands, one of which was formerly a REG. */
&& GET_CODE (recog_operand
[eopno
]) == REG
)
for (opno
= 0; opno
< noperands
; opno
++)
if ((GET_CODE (recog_operand
[opno
]) == MEM
|| op_types
[opno
] != OP_OUT
)
/* Ignore things like match_operator operands. */
&& *constraints
[opno
] != 0
&& ! (matching_operands
[opno
] == eopno
&& rtx_equal_p (recog_operand
[opno
],
&& ! safe_from_earlyclobber (recog_operand
[opno
],
while (--funny_match_index
>= 0)
recog_operand
[funny_match
[funny_match_index
].other
]
= recog_operand
[funny_match
[funny_match_index
].this];
/* If we are about to reject this, but we are not to test strictly,
try a very loose test. Only return failure if it fails also. */
return constrain_operands (insn_code_num
, -1);
/* Return 1 iff OPERAND (assumed to be a REG rtx)
is a hard reg in class CLASS when its regno is offsetted by OFFSET
and changed to mode MODE.
If REG occupies multiple hard regs, all of them must be in CLASS. */
reg_fits_class_p (operand
, class, offset
, mode
)
register enum reg_class
class;
register int regno
= REGNO (operand
);
if (regno
< FIRST_PSEUDO_REGISTER
&& TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
for (sr
= HARD_REGNO_NREGS (regno
, mode
) - 1;
if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
#endif /* REGISTER_CONSTRAINTS */