/* m68k.c All the m68020 specific stuff in one convenient, huge,
slow to compile, easy to find file.
Copyright (C) 1987 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 1, or (at your option)
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#include "struc-symbol.h"
/* This variable contains the value to write out at the beginning of
the a.out file. The 2<<16 means that this is a 68020 file instead
of an old-style 68000 file */
long omagic
= 2<<16|OMAGIC
; /* Magic byte for header file */
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful */
const char comment_chars
[] = "|";
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
.line and .file directives will appear in the pre-processed output */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
#NO_APP at the beginning of its output. */
/* Also note that '/*' will always start a comment */
const char line_comment_chars
[] = "#";
/* Chars that can be used to separate mant from exp in floating point nums */
const char EXP_CHARS
[] = "eE";
/* Chars that mean this number is a floating point constant */
const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
changed in read.c . Ideally it shouldn't have to know about it at all,
but nothing is ideal around here.
void install_gen_operand();
/* Its an arbitrary name: This means I don't approve of it */
#define TAB(x,y) (((x)<<2)+(y))
#define TABTYPE(xy) ((xy) >> 2)
/* BCC68000 is for patching in an extra jmp instruction for long offsets
on the 68000. The 68000 doesn't support long branches with branchs */
/* This table desribes how you change sizes for the various types of variable
size expressions. This version only supports two kinds. */
/* Note that calls to frag_var need to specify the maximum expansion needed */
/* This is currently 10 bytes for DBCC */
How far Forward this mode will reach:
How far Backward this mode will reach:
How many bytes this mode will add to the size of the frag
Which mode to go to if the offset won't fit in this one
{ 1, 1, 0, 0 }, /* First entries aren't used */
{ 1, 1, 0, 0 }, /* For no good reason except */
{ 1, 1, 0, 0 }, /* that the VAX doesn't either */
{ (127), (-128), 0, TAB(BRANCH
,SHORT
)},
{ (32767), (-32768), 2, TAB(BRANCH
,LONG
) },
{ 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
{ (32767), (-32768), 2, TAB(FBRANCH
,LONG
)},
{ 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
{ (32767), (-32768), 2, TAB(PCREL
,LONG
)},
{ (127), (-128), 0, TAB(BCC68000
,SHORT
)},
{ (32767), (-32768), 2, TAB(BCC68000
,LONG
) },
{ 0, 0, 6, 0 }, /* jmp long space */
{ 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
{ (32767), (-32768), 2, TAB(DBCC
,LONG
) },
{ 0, 0, 10, 0 }, /* bra/jmp long space */
{ 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
{ 32767, -32768, 2, TAB(PCLEA
,LONG
) },
void s_data1(), s_data2(), s_even(), s_space();
void s_proc(), float_cons();
/* These are the machine dependent pseudo-ops. These are included so
the assembler can work on the output from the SUN C compiler, which
/* This table describes all the machine specific pseudo-ops the assembler
has to support. The fields are:
pseudo-op name without dot
function to call to execute this pseudo-op
Integer arg to pass to the function
const pseudo_typeS md_pseudo_table
[] = {
/* #define isbyte(x) ((x)>=-128 && (x)<=127) */
/* #define isword(x) ((x)>=-32768 && (x)<=32767) */
#define issbyte(x) ((x)>=-128 && (x)<=127)
#define isubyte(x) ((x)>=0 && (x)<=255)
#define issword(x) ((x)>=-32768 && (x)<=32767)
#define isuword(x) ((x)>=0 && (x)<=65535)
#define isbyte(x) ((x)>=-128 && (x)<=255)
#define isword(x) ((x)>=-32768 && (x)<=65535)
extern char *input_line_pointer
;
/* Operands we can parse: (And associated modes)
reg: address or data register
apc: address register, PC, ZPC or empty string
sz: w or l if omitted, l assumed
scale: 1 2 4 or 8 if omitted, 1 assumed
2.? AINDR areg@ --> *(areg)
3.? AINC areg@+ --> *(areg++)
4.? ADEC areg@- --> *(--areg)
5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
6.? AINDX apc@(reg:sz:scale) --> same, with num=0
6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
7.0 ABSL num:sz --> *(num)
num --> *(num) (sz L assumed)
*** MSCR otherreg --> Magic
5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
a1@(5,d2:w:1) @(45,d6:l:4)
#name@(numw) -->turn into PC rel mode
apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
/* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
8-15==addr reg for operands that take both types */
#define DATA 1 /* 1- 8 == data registers 0-7 */
#define ADDR (DATA+8) /* 9-16 == address regs 0-7 */
#define FPREG (ADDR+8) /* 17-24 Eight FP registers */
#define COPNUM (FPREG+8) /* 25-32 Co-processor #1-#8 */
#define PC (COPNUM+8) /* 33 Program counter */
#define ZPC (PC+1) /* 34 Hack for Program space, but 0 addressing */
#define SR (ZPC+1) /* 35 Status Reg */
#define CCR (SR+1) /* 36 Condition code Reg */
/* These have to be in order for the movec instruction to work. */
#define USP (CCR+1) /* 37 User Stack Pointer */
#define ISP (USP+1) /* 38 Interrupt stack pointer */
#define SFC (ISP+1) /* 39 */
#define DFC (SFC+1) /* 40 */
#define CACR (DFC+1) /* 41 */
#define VBR (CACR+1) /* 42 */
#define CAAR (VBR+1) /* 43 */
#define MSP (CAAR+1) /* 44 */
#define FPI (MSP+1) /* 45 */
#define FPS (FPI+1) /* 46 */
#define FPC (FPS+1) /* 47 */
* these defines should be in m68k.c but
* i put them here to keep all the m68851 stuff
* JF--Make sure these #s don't clash with the ones in m68k.c
#define TC (FPC+1) /* 48 */
#define DRP (TC+1) /* 49 */
#define SRP (DRP+1) /* 50 */
#define CRP (SRP+1) /* 51 */
#define CAL (CRP+1) /* 52 */
#define VAL (CAL+1) /* 53 */
#define SCC (VAL+1) /* 54 */
#define AC (SCC+1) /* 55 */
#define BAD (AC+1) /* 56,57,58,59, 60,61,62,63 */
#define BAC (BAD+8) /* 64,65,66,67, 68,69,70,71 */
#define PSR (BAC+8) /* 72 */
#define PCSR (PSR+1) /* 73 */
/* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
/* JF these tables here are for speed at the expense of size */
/* You can replace them with the #if 0 versions if you really
need space and don't mind it running a bit slower */
static char mklower_table
[256];
#define mklower(c) (mklower_table[(unsigned char)(c)])
static char notend_table
[256];
static char alt_notend_table
[256];
#define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
alt_notend_table[(unsigned char)(s[1])])))
#define mklower(c) (isupper(c) ? tolower(c) : c)
short e_siz
; /* 0== default 1==short/byte 2==word 3==long */
/* Internal form of an operand. */
char *error
; /* Couldn't parse it */
int mode
; /* What mode this instruction is in. */
unsigned long int reg
; /* Base register */
int ireg
; /* Index register */
int isiz
; /* 0==unspec 1==byte(?) 2==short 3==long */
int imul
; /* Multipy ireg by this (1,2,4,or 8) */
/* internal form of a 68020 instruction */
char *args
; /* list of opcode info */
int numo
; /* Number of shorts in opcode */
struct m68k_op operands
[6];
int nexp
; /* number of exprs in use */
struct m68k_exp exprs
[4];
int nfrag
; /* Number of frags we have to produce */
int fragoff
; /* Where in the current opcode[] the frag ends */
int nrel
; /* Num of reloc strucs in use */
} reloc
[5]; /* Five is enough??? */
struct m68_it the_ins
; /* the instruction being assembled */
/* Macros for adding things to the m68_it struct */
#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
/* Like addword, but goes BEFORE general operands */
#define insop(w) {int z;\
for(z=the_ins.numo;z>opcode->m_codenum;--z)\
the_ins.opcode[z]=the_ins.opcode[z-1];\
for(z=0;z<the_ins.nrel;z++)\
the_ins.opcode[opcode->m_codenum]=w;\
#define add_exp(beg,end) (\
the_ins.exprs[the_ins.nexp].e_beg=beg,\
the_ins.exprs[the_ins.nexp].e_end=end,\
&the_ins.exprs[the_ins.nexp++]\
/* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
#define add_fix(width,exp,pc_rel) {\
the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
(((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
the_ins.reloc[the_ins.nrel].add=adds((exp));\
the_ins.reloc[the_ins.nrel].sub=subs((exp));\
the_ins.reloc[the_ins.nrel].off=offs((exp));\
the_ins.reloc[the_ins.nrel].wid=width;\
the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
#define add_frag(add,off,type) {\
the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
the_ins.fragb[the_ins.nfrag].fadd=add;\
the_ins.fragb[the_ins.nfrag].foff=off;\
the_ins.fragb[the_ins.nfrag++].fragty=type;\
#define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
#define seg(exp) ((exp)->e_exp.X_seg)
#define adds(exp) ((exp)->e_exp.X_add_symbol)
#define subs(exp) ((exp)->e_exp.X_subtract_symbol)
#define offs(exp) ((exp)->e_exp.X_add_number)
struct m68_incant
*m_next
;
#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
#define gettwo(x) (((x)->m_opcode)&0xffff)
/* JF modified this to handle cases where the first part of a symbol name
if (c4
>= '0' && c4
<= '7') {
if (c4
>= '0' && c4
<= '7') {
if (c2
== 'a' && c3
== 'l') {
/* This supports both CCR and CC as the ccr reg. */
} else if(c2
=='a' && (c3
=='a' || c3
=='c') && c4
=='r') {
ret
= c3
=='a' ? CAAR
: CACR
;
else if (c2
== 'r' && c3
== 'p') {
} else if(c2
=='f' && c3
=='c') {
else if (c2
== 'r' && c3
== 'p') {
if(c3
== 's' && c4
=='r') {
else if (c2
== 's' && c3
== 'r') {
if (c2
== 'c' && c3
== 'c') {
} else if (c2
== 'r' && c3
== 'p') {
} else if(c2
=='f' && c3
=='c') {
if (c2
== 'a' && c3
== 'l') {
if(isalnum(ccp
[0][n
]) || ccp
[0][n
]=='_')
#define SKIP_WHITE() { str++; if(*str==' ') str++;}
register struct m68k_op
*opP
;
/* Find the end of the string */
opP
->error
="Missing operand";
for(strend
=str
;*strend
;strend
++)
/* Guess what: A constant. Shar and enjoy */
opP
->con1
=add_exp(str
,strend
);
if((i
==FAIL
|| *str
!='\0') && *str
!='@') {
if(i
!=FAIL
&& (*str
=='/' || *str
=='-')) {
return get_regs(i
,str
,opP
);
if(stmp
=index(str
,'@')) {
opP
->con1
=add_exp(str
,stmp
-1);
if(*stmp
++!='(' || *strend
--!=')') {
opP
->error
="Malformed operand";
opP
->con2
=add_exp(stmp
,strend
);
if(i
==FAIL
) opP
->mode
=AMIND
;
opP
->con1
=add_exp(str
,strend
);
if(i
>=DATA
+0 && i
<=DATA
+7)
else if(i
>=ADDR
+0 && i
<=ADDR
+7)
if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
&& i
!=ZPC
&& i
!=FAIL
) { /* Can't indirect off non address regs */
opP
->error
="Invalid indirect register";
opP
->error
="Junk after indirect";
/* Some kind of indexing involved. Lets find out how bad it is */
/* Didn't start with an index reg, maybe its offset or offset,reg */
opP->error="Specified size isn't :w or :l";
opP->con1=add_exp(beg_str,str-4);
opP
->con1
=add_exp(beg_str
,str
-2);
/* Should be offset,reg */
opP
->error
="Malformed index reg";
/* We've now got offset) offset,reg) or reg) */
/* Th-the-thats all folks */
if(opP
->reg
==FAIL
) opP
->mode
=AINDX
; /* Other form of indirect */
else if(opP
->ireg
==FAIL
) opP
->mode
=AOFF
;
/* Next thing had better be another @ */
if(*str
!='@' || str
[1]!='(') {
opP
->error
="junk after indirect";
opP
->error
="Two index registers! not allowed!";
opP
->con2
=add_exp(beg_str
,str
-2);
opP
->error
="Can't have two index regs";
opP
->error
="malformed index reg";
} else if(opP
->ireg
!=FAIL
)
opP
->error
="Junk after indirect";
#define SKIP_W() { ss++; if(*ss==' ') ss++;}
if(!(i
>=DATA
+0 && i
<=ADDR
+7)) { /* if i is not DATA or ADDR reg */
opP
->error
="Missing : in index register";
opP
->error
="Index register size spec not :w or :l";
opP
->error
="index multiplier not 1, 2, 4 or 8";
#ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
bzero(&thark
,sizeof(thark
));
if(!m68k_ip_op(buf
,&thark
)) printf("FAIL:");
printf("op1 error %s in %s\n",thark
.error
,buf
);
printf("mode %d, reg %d, ",thark
.mode
,thark
.reg
);
printf("Constant: '%.*s',",1+thark
.e_const
-thark
.b_const
,thark
.b_const
);
printf("ireg %d, isiz %d, imul %d ",thark
.ireg
,thark
.isiz
,thark
.imul
);
printf("Iadd: '%.*s'",1+thark
.e_iadd
-thark
.b_iadd
,thark
.b_iadd
);
static struct hash_control
* op_hash
= NULL
; /* handle of the OPCODE hash table
NULL means any use before m68_ip_begin()
* This converts a string into a 68k instruction.
* The string must be a bare single instruction in sun format
* with RMS-style 68020 indirects
* It provides some error messages: at most one fatal error message (which
* stops the scan) and at most one warning message for each operand.
* The 68k instruction is returned in exploded form, since we have no
* knowledge of how you parse (or evaluate) your expressions.
* We do however strip off and decode addressing modes and operation
* This function's value is a string. If it is not "" then an internal
* logic error was found: read this code to assign meaning to the string.
* No argument string should generate such an error string:
* it means a bug in our code, not in the user's text.
* You MUST have called m86_ip_begin() once and m86_ip_end() never before using
/* JF this function no longer returns a useful value. Sorry */
register struct m68k_op
*opP
;
register struct m68_incant
*opcode
;
instring
++; /* skip leading whitespace */
/* Scan up to end of operation-code, which MUST end in end-of-string
for (p
= instring
; *p
!= '\0'; p
++)
the_ins
.error
= "No operator";
the_ins
.opcode
[0] = NULL
;
/* p now points to the end of the opcode name, probably whitespace.
make sure the name is null terminated by clobbering the whitespace,
look it up in the hash table, then fix it back. */
opcode
= (struct m68_incant
*)hash_find (op_hash
, instring
);
the_ins
.error
= "Unknown operator";
the_ins
.opcode
[0] = NULL
;
/* found a legitimate opcode, start matching operands */
for(opP
= &the_ins
.operands
[0];*p
;opP
++) {
p
= crack_operand (p
, opP
);
the_ins
.error
=opP
->error
;
opsfound
=opP
- &the_ins
.operands
[0];
/* This ugly hack is to support the floating pt opcodes in their standard form */
/* Essentially, we fake a first enty of type COP#1 */
if(opcode
->m_operands
[0]=='I') {
the_ins
.operands
[n
]=the_ins
.operands
[n
-1];
/* bcopy((char *)(&the_ins.operands[0]),(char *)(&the_ins.operands[1]),opsfound*sizeof(the_ins.operands[0])); */
bzero((char *)(&the_ins
.operands
[0]),sizeof(the_ins
.operands
[0]));
the_ins
.operands
[0].mode
=MSCR
;
the_ins
.operands
[0].reg
=COPNUM
; /* COP #1 */
/* We've got the operands. Find an opcode that'll
if(opsfound
!=opcode
->m_opnum
)
else for(s
=opcode
->m_operands
,opP
= &the_ins
.operands
[0];*s
&& !losing
;s
+=2,opP
++) {
/* Warning: this switch is huge! */
/* I've tried to organize the cases into this order:
non-alpha first, then alpha by letter. lower-case goes directly
before uppercase counterpart. */
/* Code with multiple case ...: gets sorted by the lowest case ...
it belongs to. I hope this makes sense. */
if(opP
->mode
==MSCR
|| opP
->mode
==IMMED
||
opP
->mode
==DREG
|| opP
->mode
==AREG
|| opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==REGLST
)
if(s
[1]=='b' && !isbyte(t
))
else if(s
[1]=='w' && !isword(t
))
if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
if(opP
->mode
==MSCR
|| opP
->reg
==PC
||
opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
opP
->mode
==AREG
|| opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
||
opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==REGLST
)
if(opP
->mode
==MSCR
|| opP
->mode
==REGLST
)
if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==IMMED
|| opP
->mode
==REGLST
)
if(opP
->mode
==MSCR
|| opP
->mode
==AREG
|| opP
->mode
==REGLST
)
if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==IMMED
|| opP
->reg
==PC
||
opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
opP
->mode
==IMMED
|| opP
->mode
==REGLST
)
case '~': /* For now! (JF FOO is this right?) */
if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
opP
->mode
==AREG
|| opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
if(opP
->mode
!=MSCR
|| opP
->reg
!=CCR
)
case 'd': /* FOO This mode is a KLUDGE!! */
if(opP
->mode
!=AOFF
&& (opP
->mode
!=ABSL
||
opP
->con1
->e_beg
[0]!='(' || opP
->con1
->e_end
[0]!=')'))
if(opP
->mode
!=MSCR
|| opP
->reg
<(FPREG
+0) || opP
->reg
>(FPREG
+7))
if(opP
->mode
!=MSCR
|| opP
->reg
<COPNUM
||
if(opP
->mode
!=MSCR
|| opP
->reg
<USP
|| opP
->reg
>MSP
)
if(opP
->mode
==DREG
|| opP
->mode
==AREG
|| opP
->mode
==FPREG
) {
opP
->reg
=1<<(opP
->reg
-DATA
);
} else if(opP
->mode
!=REGLST
) {
} else if(s
[1]=='8' && opP
->reg
&0x0FFffFF)
else if(s
[1]=='3' && opP
->reg
&0x7000000)
if(!issbyte(t
) || isvar(opP
->con1
))
if(opP
->mode
!=DREG
&& opP
->mode
!=IMMED
)
if(t
<1 || t
>8 || isvar(opP
->con1
))
if(opP
->mode
!=DREG
&& opP
->mode
!=AREG
)
if(opP
->mode
!=MSCR
|| !(opP
->reg
==FPI
|| opP
->reg
==FPS
|| opP
->reg
==FPC
))
if(opP
->mode
!=MSCR
|| opP
->reg
!=SR
)
if(opP
->mode
!=MSCR
|| opP
->reg
!=USP
)
/* JF these are out of order. We could put them
in order if we were willing to put up with
bunches of #ifdef m68851s in the code */
/* Memory addressing mode used by pflushr */
if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
opP
->mode
==AREG
|| opP
->mode
==REGLST
)
if (opP
->mode
!= MSCR
|| (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
if (opP
->mode
!= MSCR
|| (opP
->reg
!= TC
&& opP
->reg
!= CAL
&&
opP
->reg
!= VAL
&& opP
->reg
!= SCC
&& opP
->reg
!= AC
))
if (opP
->mode
!= MSCR
|| (opP
->reg
!= DRP
&& opP
->reg
!= SRP
&&
(!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+7) &&
!(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+7)))
as_fatal("Internal error: Operand mode %c unknown",*s
);
if(!opcode
) { /* Fell off the end */
the_ins
.error
="instruction/operands mismatch";
the_ins
.args
=opcode
->m_operands
;
the_ins
.numargs
=opcode
->m_opnum
;
the_ins
.numo
=opcode
->m_codenum
;
the_ins
.opcode
[0]=getone(opcode
);
the_ins
.opcode
[1]=gettwo(opcode
);
for(s
=the_ins
.args
,opP
= &the_ins
.operands
[0];*s
;s
+=2,opP
++) {
/* This switch is a doozy.
What the first step; its a big one! */
if(index("bwl",s
[1])) nextword
=get_num(opP
->con1
,80);
else nextword
=nextword
=get_num(opP
->con1
,0);
add_fix(s
[1],opP
->con1
,0);
opP
->error
="operand out of range";
opP
->error
="operand out of range";
as_fatal("Internal error: Can't decode %c%c",*s
,s
[1]);
/* We gotta put out some float */
if(seg(opP
->con1
)!=SEG_BIG
) {
gen_to_words(words
,baseo
,(long int)outro
);
for(wordp
=words
;baseo
--;wordp
++)
as_warn("Bignum assumed to be binary bit-pattern");
if(offs(opP
->con1
)>baseo
) {
as_warn("Bignum too big for %c format; truncated",s
[1]);
for(wordp
=generic_bignum
+offs(opP
->con1
)-1;offs(opP
->con1
)--;--wordp
)
gen_to_words(words
,baseo
,(long int)outro
);
for(wordp
=words
;baseo
--;wordp
++)
tmpreg
=opP
->reg
-DATA
; /* 0.dreg */
tmpreg
=0x08+opP
->reg
-ADDR
; /* 1.areg */
tmpreg
=0x10+opP
->reg
-ADDR
; /* 2.areg */
tmpreg
=0x20+opP
->reg
-ADDR
; /* 4.areg */
tmpreg
=0x18+opP
->reg
-ADDR
; /* 3.areg */
nextword
=get_num(opP
->con1
,80);
/* Force into index mode. Hope this works */
/* We do the first bit for 32-bit displacements,
and the second bit for 16 bit ones. It is
possible that we should make the default be
WORD instead of LONG, but I think that'd
break GCC, so we put up with a little
inefficiency for the sake of working output.
&& ( ( opP
->con1
->e_siz
==0
|| opP
->con1
->e_siz
==3))) {
tmpreg
=0x30+opP
->reg
-ADDR
; /* 6.areg */
add_frag(adds(opP
->con1
),
add_fix('l',opP
->con1
,1);
tmpreg
=0x28+opP
->reg
-ADDR
; /* 5.areg */
add_fix('w',opP
->con1
,1);
add_fix('w',opP
->con1
,0);
baseo
=get_num(opP
->con1
,80);
outro
=get_num(opP
->con2
,80);
/* Figure out the 'addressing mode' */
/* Also turn on the BASE_DISABLE bit, if needed */
if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
} else if(opP
->reg
==FAIL
) {
tmpreg
=0x30; /* 6.garbage */
} else tmpreg
=0x30+opP
->reg
-ADDR
; /* 6.areg */
siz1
= (opP
->con1
) ? opP
->con1
->e_siz
: 0;
siz2
= (opP
->con2
) ? opP
->con2
->e_siz
: 0;
/* Index register stuff */
if(opP
->ireg
>=DATA
+0 && opP
->ireg
<=ADDR
+7) {
nextword
|=(opP
->ireg
-DATA
)<<12;
if(opP
->isiz
==0 || opP
->isiz
==3)
case 2: nextword
|=0x200; break;
case 4: nextword
|=0x400; break;
case 8: nextword
|=0x600; break;
/* Must be INDEX, with an index
register. Address register
cannot be ZERO-PC, and either
:b was forced, or we know
&& !isvar(opP
->con1
)))) {
add_fix('B',opP
->con1
,0);
nextword
|=0x40; /* No index reg */
/* If the guy specified a width, we assume that
it is wide enough. Maybe it isn't. Ifso, we lose
if(isvar(opP
->con1
) || !issword(baseo
)) {
as_warn("Byte dispacement won't work. Defaulting to :w");
/* Figure out innner displacement stuff */
if(isvar(opP
->con2
) || !issword(outro
)) {
as_warn("Byte dispacement won't work. Defaulting to :w");
if(opP
->mode
==APODX
) nextword
|=0x04;
else if(opP
->mode
==AMIND
) nextword
|=0x40;
if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
add_fix(siz1
==3 ? 'l' : 'w',opP
->con1
,1);
opP
->con1
->e_exp
.X_add_number
+=6;
add_fix(siz1
==3 ? 'l' : 'w',opP
->con1
,0);
if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
add_fix(siz2
==3 ? 'l' : 'w',opP
->con2
,1);
opP
->con1
->e_exp
.X_add_number
+=6;
add_fix(siz2
==3 ? 'l' : 'w',opP
->con2
,0);
nextword
=get_num(opP
->con1
,80);
switch(opP
->con1
->e_siz
) {
as_warn("Unknown size for absolute reference");
if(!isvar(opP
->con1
) && issword(offs(opP
->con1
))) {
/* Don't generate pc relative code
seg(opP
->con1
)==SEG_TEXT
&&
add_frag(adds(opP
->con1
),
case 3: /* Fall through into long */
add_fix('l',opP
->con1
,0);
tmpreg
=0x39; /* 7.1 mode */
add_fix('w',opP
->con1
,0);
tmpreg
=0x38; /* 7.0 mode */
as_bad("unknown/incorrect operand");
install_gen_operand(s
[1],tmpreg
);
switch(s
[1]) { /* JF: I hate floating point! */
tmpreg
=get_num(opP
->con1
,tmpreg
);
add_fix(s
[1],opP
->con1
,0);
case 'b': /* Danger: These do no check for
certain types of overflow.
opP
->error
="out of range";
the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
opP
->error
="out of range";
the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
insop(tmpreg
); /* Because of the way insop works, we put these two out backwards */
the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
install_operand(s
[1],tmpreg
);
as_fatal("Internal error: Unknown mode #%c",s
[1]);
install_operand(s
[1],opP
->reg
-ADDR
);
tmpreg
=get_num(opP
->con1
,80);
if(opP
->con1
->e_siz
) { /* Deal with fixed size stuff by hand */
switch(opP
->con1
->e_siz
) {
add_fix('b',opP
->con1
,1);
add_fix('w',opP
->con1
,1);
add_fix('l',opP
->con1
,1);
as_fatal("Bad size for expression %d",opP
->con1
->e_siz
);
} else if(subs(opP
->con1
)) {
the_ins
.opcode
[the_ins
.numo
-1]|=0xff;
add_fix('l',opP
->con1
,1);
} else if(adds(opP
->con1
)) {
(the_ins
.opcode
[0] >= 0x6200) &&
(the_ins
.opcode
[0] <= 0x6f00)) {
add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(BCC68000
,SZ_UNDEF
));
add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(BRANCH
,SZ_UNDEF
));
/* JF: This is the WRONG thing to do
add_frag((symbolS *)0,offs(opP->con1),TAB(BRANCH,BYTE)); */
the_ins
.opcode
[the_ins
.numo
-1]|=0xff;
add_fix('l',opP
->con1
,1);
/* check for DBcc instruction */
if ((the_ins
.opcode
[0] & 0xf0f8) ==0x50c8) {
/* size varies if patch */
/* needed for long form */
add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(DBCC
,SZ_UNDEF
));
opP
->con1
->e_exp
.X_add_number
+=2;
add_fix('w',opP
->con1
,1);
switch(opP
->con1
->e_siz
) {
the_ins
.opcode
[the_ins
.numo
-1]|=0x40;
add_fix('l',opP
->con1
,1);
as_bad("Bad size for offset, must be word or long");
} else if(subs(opP
->con1
)) {
add_fix('l',opP
->con1
,1);
add_frag((symbolS
*)0,(long)0,TAB(FBRANCH
,LONG
));
} else if(adds(opP
->con1
)) {
add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(FBRANCH
,SZ_UNDEF
));
/* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
the_ins
.opcode
[the_ins
.numo
-1]|=0x40;
add_fix('l',opP
->con1
,1);
as_fatal("Internal error: operand type B%c unknown",s
[1]);
case 'C': /* Ignore it */
case 'd': /* JF this is a kludge */
install_operand('s',opP
->reg
-ADDR
);
opP
->con1
->e_end
-=4; /* point to the , */
baseo
=m68k_reg_parse(&tmpP
);
if(baseo
<ADDR
+0 || baseo
>ADDR
+7) {
as_bad("Unknown address reg, using A0");
install_operand('s',baseo
);
tmpreg
=get_num(opP
->con1
,80);
as_warn("Expression out of range, using 0");
install_operand(s
[1],opP
->reg
-DATA
);
install_operand(s
[1],opP
->reg
-FPREG
);
tmpreg
=1+opP
->reg
-COPNUM
;
install_operand(s
[1],tmpreg
);
install_operand(s
[1],tmpreg
);
tmpreg
=get_num(opP
->con1
,55);
install_operand(s
[1],tmpreg
&0x7f);
as_bad("Floating point register in register list");
insop(reverse_16_bits(tmpreg
));
as_bad("Wrong register in floating-point reglist");
install_operand(s
[1],reverse_8_bits(tmpreg
>>16));
as_bad("Floating point register in register list");
as_bad("incorrect register in reglist");
install_operand(s
[1],tmpreg
>>24);
as_bad("wrong register in floating-point reglist");
install_operand(s
[1],tmpreg
>>16);
install_operand(s
[1],get_num(opP
->con1
,60));
tmpreg
= (opP
->mode
==DREG
)
: (get_num(opP
->con1
,40)&0x1F);
install_operand(s
[1],tmpreg
);
tmpreg
=get_num(opP
->con1
,10);
install_operand(s
[1],tmpreg
);
/* This depends on the fact that ADDR registers are
eight more than their corresponding DATA regs, so
the result will have the ADDR_REG bit set */
install_operand(s
[1],opP
->reg
-DATA
);
if(opP
->reg
==FPI
) tmpreg
=0x1;
else if(opP
->reg
==FPS
) tmpreg
=0x2;
else if(opP
->reg
==FPC
) tmpreg
=0x4;
install_operand(s
[1],tmpreg
);
case 'S': /* Ignore it */
install_operand(s
[1],get_num(opP
->con1
,30));
case 'U': /* Ignore it */
/* JF: These are out of order, I fear. */
install_operand(s
[1],tmpreg
);
install_operand(s
[1],tmpreg
);
install_operand(s
[1],tmpreg
);
case BAD
: case BAD
+1: case BAD
+2: case BAD
+3:
case BAD
+4: case BAD
+5: case BAD
+6: case BAD
+7:
tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
case BAC
: case BAC
+1: case BAC
+2: case BAC
+3:
case BAC
+4: case BAC
+5: case BAC
+6: case BAC
+7:
tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
install_operand(s
[1], tmpreg
);
as_fatal("Internal error: Operand type %c unknown",s
[0]);
/* By the time whe get here (FINALLY) the_ins contains the complete
instruction, ready to be emitted. . . */
/* 26, 25, 24, 23-16, 15-8, 0-7 */
/* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
unsigned long int cur_regs
= 0;
#define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
else if(x==FPS) cur_regs|=(1<<25);\
else if(x==FPC) cur_regs|=(1<<26);\
else cur_regs|=(1<<(x-1)); }
reg2
=m68k_reg_parse(&str
);
if(reg2
<DATA
|| reg2
>=FPREG
+8 || reg1
==FPI
|| reg1
==FPS
|| reg1
==FPC
) {
opP
->error
="unknown register in register list";
opP
->error
="unknow character in register list";
/* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
reg1
=m68k_reg_parse(&str
);
if((reg1
<DATA
|| reg1
>=FPREG
+8) && !(reg1
==FPI
|| reg1
==FPS
|| reg1
==FPC
)) {
opP
->error
="unknown register in register list";
0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
install_operand(mode
,val
)
the_ins
.opcode
[0]|=val
& 0xFF; /* JF FF is for M kludge */
the_ins
.opcode
[0]|=val
<<9;
the_ins
.opcode
[1]|=val
<<12;
the_ins
.opcode
[1]|=val
<<6;
the_ins
.opcode
[2]|=val
<<12;
the_ins
.opcode
[2]|=val
<<6;
/* DANGER! This is a hack to force cas2l and cas2w cmds
to be three words long! */
the_ins
.opcode
[1]|=val
<<7;
the_ins
.opcode
[1]|=val
<<10;
the_ins
.opcode
[1]|=val
<<5;
the_ins
.opcode
[1]|=(val
<<10)|(val
<<7);
the_ins
.opcode
[1]|=(val
<<12)|val
;
the_ins
.opcode
[0]|=val
=0xff;
the_ins
.opcode
[0]|=val
<<9;
the_ins
.numo
++; /* What a hack */
the_ins
.opcode
[1]|=val
<<4;
install_gen_operand(mode
,val
)
/* This is a kludge!!! */
the_ins
.opcode
[0]|=(val
&0x07)<<9|(val
&0x38)<<3;
/* more stuff goes here */
register struct m68k_op
*opP
;
for(parens
=0;*str
&& (parens
>0 || notend(str
));str
++) {
if(!parens
) { /* ERROR */
if(!*str
&& parens
) { /* ERROR */
if(m68k_ip_op(beg_str
,opP
)==FAIL
) {
c
= *++str
; /* JF bitfield hack */
as_bad("Missing operand");
/* See the comment up above where the #define notend(... is */
/* This kludge here is for the division cmd, which is a kludge */
if(index("aAdD#",s
[1])) return 0;
/* This is the guts of the machine-dependent assembler. STR points to a
machine dependent instruction. This funciton is supposed to emit
the frags/bytes it assembles to.
bzero((char *)(&the_ins
),sizeof(the_ins
)); /* JF for paranoia sake */
for(n
=the_ins
.numargs
;n
;--n
)
if(the_ins
.operands
[n
].error
) {
er
=the_ins
.operands
[n
].error
;
as_bad("\"%s\" -- Statement '%s' ignored",er
,str
);
if(the_ins
.nfrag
==0) { /* No frag hacking involved; just put it out */
toP
=frag_more(2*the_ins
.numo
);
fromP
= &the_ins
.opcode
[0];
for(m
=the_ins
.numo
;m
;--m
) {
md_number_to_chars(toP
,(long)(*fromP
),2);
/* put out symbol-dependent info */
for(m
=0;m
<the_ins
.nrel
;m
++) {
switch(the_ins
.reloc
[m
].wid
) {
as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins
.reloc
[m
].wid
);
(toP
-frag_now
->fr_literal
)-the_ins
.numo
*2+the_ins
.reloc
[m
].n
,
/* There's some frag hacking */
for(n
=0,fromP
= &the_ins
.opcode
[0];n
<the_ins
.nfrag
;n
++) {
if(n
==0) wid
=2*the_ins
.fragb
[n
].fragoff
;
else wid
=2*(the_ins
.numo
-the_ins
.fragb
[n
-1].fragoff
);
md_number_to_chars(toP
,(long)(*fromP
),2);
for(m
=0;m
<the_ins
.nrel
;m
++) {
if((the_ins
.reloc
[m
].n
)>= 2*shorts_this_frag
/* 2*the_ins.fragb[n].fragoff */) {
the_ins
.reloc
[m
].n
-= 2*shorts_this_frag
/* 2*the_ins.fragb[n].fragoff */;
wid
=the_ins
.reloc
[m
].wid
;
wid
= (wid
=='b') ? 1 : (wid
=='w') ? 2 : (wid
=='l') ? 4 : 4000;
(toP
-frag_now
->fr_literal
)-the_ins
.numo
*2+the_ins
.reloc
[m
].n
,
know(the_ins
.fragb
[n
].fadd
);
(void)frag_var(rs_machine_dependent
,10,0,(relax_substateT
)(the_ins
.fragb
[n
].fragty
),
the_ins
.fragb
[n
].fadd
,the_ins
.fragb
[n
].foff
,to_beg_P
);
n
=(the_ins
.numo
-the_ins
.fragb
[n
-1].fragoff
);
toP
=frag_more(n
*sizeof(short));
md_number_to_chars(toP
,(long)(*fromP
),2);
for(m
=0;m
<the_ins
.nrel
;m
++) {
wid
=the_ins
.reloc
[m
].wid
;
wid
= (wid
=='b') ? 1 : (wid
=='w') ? 2 : (wid
=='l') ? 4 : 4000;
(the_ins
.reloc
[m
].n
+ toP
-frag_now
->fr_literal
)-/* the_ins.numo */ shorts_this_frag
*2,
/* This function is called once, at assembler startup time. This should
set up all the tables, etc that the MD part of the assembler needs
* md_begin -- set up hash tables with 68000 instructions.
* similar to what the vax assembler does. ---phr
/* RMS claims the thing to do is take the m68k-opcode.h table, and make
a copy of it at runtime, adding in the information we want but isn't
there. I think it'd be better to have an awk script hack the table
at compile time. Or even just xstr the table and use it as-is. But
my lord ghod hath spoken, so we do it this way. Excuse the ugly var
register struct m68k_opcode
*ins
;
register struct m68_incant
*hack
,
register char *retval
= 0; /* empty string, or error msg text */
if ((op_hash
= hash_new()) == NULL
)
as_fatal("Virtual memory exhausted");
obstack_begin(&robyn
,4000);
for (ins
= m68k_opcodes
; ins
< endop
; ins
++) {
hack
=slak
=(struct m68_incant
*)obstack_alloc(&robyn
,sizeof(struct m68_incant
));
slak
->m_operands
=ins
->args
;
slak
->m_opnum
=strlen(slak
->m_operands
)/2;
slak
->m_opcode
=ins
->opcode
;
slak
->m_codenum
=((ins
->match
)&0xffffL
) ? 2 : 1;
if((ins
+1)!=endop
&& !strcmp(ins
->name
,(ins
+1)->name
)) {
slak
->m_next
=(struct m68_incant
*)
obstack_alloc(&robyn
,sizeof(struct m68_incant
));
retval
= hash_insert (op_hash
, ins
->name
,(char *)hack
);
/* Didn't his mommy tell him about null pointers? */
as_fatal("Internal Error: Can't hash %s: %s",ins
->name
,retval
);
for (i
= 0; i
< sizeof(mklower_table
) ; i
++)
mklower_table
[i
] = (isupper(c
= (char) i
)) ? tolower(c
) : c
;
for (i
= 0 ; i
< sizeof(notend_table
) ; i
++) {
alt_notend_table
['a'] = 1;
alt_notend_table
['A'] = 1;
alt_notend_table
['d'] = 1;
alt_notend_table
['D'] = 1;
alt_notend_table
['#'] = 1;
alt_notend_table
['f'] = 1;
alt_notend_table
['F'] = 1;
alt_notend_table
[REGISTER_PREFIX
] = 1;
#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
|| (*s == ':' && index("aAdD#", s[1]))) \
/* This funciton is called once, before the assembler exits. It is
supposed to do any final cleanup for this part of the assembler.
/* Equal to MAX_PRECISION in atof-ieee.c */
/* Turn a string in input_line_pointer into a floating point constant of type
type, and store the appropriate bytes in *litP. The number of LITTLENUMS
emitted is stored in *sizeP . An error message is returned, or NULL on OK.
LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
return "Bad call to MD_ATOF()";
t
=atof_ieee(input_line_pointer
,type
,words
);
*sizeP
=prec
* sizeof(LITTLENUM_TYPE
);
for(wordP
=words
;prec
--;) {
md_number_to_chars(litP
,(long)(*wordP
++),sizeof(LITTLENUM_TYPE
));
litP
+=sizeof(LITTLENUM_TYPE
);
return ""; /* Someone should teach Dean about null pointers */
/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
for use in the a.out file, and stores them in the array pointed to by buf.
This knows about the endian-ness of the target machine and does
THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
2 (short) and 4 (long) Floating numbers are put out as a series of
LITTLENUMS (shorts, here at least)
md_number_to_chars(buf
,val
,n
)
md_number_to_imm(buf
,val
,n
)
md_number_to_disp(buf
,val
,n
)
md_number_to_field(buf
,val
,fix
)
/* *fragP has been relaxed to its final size, and now needs to have
the bytes inside it modified to conform to the new size There is UGLY
/* Address in gas core of the place to store the displacement. */
register char *buffer_address
= fragP
-> fr_fix
+ fragP
-> fr_literal
;
/* Address in object code of the displacement. */
register int object_address
= fragP
-> fr_fix
+ fragP
-> fr_address
;
/* The displacement of the address, from current location. */
disp
= (fragP
->fr_symbol
->sy_value
+ fragP
->fr_offset
) - object_address
;
switch(fragP
->fr_subtype
) {
as_bad("short branch with zero offset: use :w");
fragP
->fr_opcode
[1]=disp
;
case TAB(BCC68000
,SHORT
):
fragP
->fr_opcode
[1]=0x00;
if(fragP
->fr_opcode
[0]==0x61) {
fragP
->fr_opcode
[0]= 0x4E;
fragP
->fr_opcode
[1]= 0xB9; /* JBSR with ABSL LONG offset */
subseg_change(SEG_TEXT
, 0);
fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0);
} else if(fragP
->fr_opcode
[0]==0x60) {
fragP
->fr_opcode
[0]= 0x4E;
fragP
->fr_opcode
[1]= 0xF9; /* JMP with ABSL LONG offset */
subseg_change(SEG_TEXT
, 0);
fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
,0);
as_bad("Long branch offset not supported.");
fragP
->fr_opcode
[1]=0xff;
/* only Bcc 68000 instructions can come here */
/* change bcc into b!cc/jmp absl long */
fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
fragP
->fr_opcode
[1] = 0x6; /* branch offset = 6 */
/* JF: these used to be fr_opcode[2,3], but they may be in a
different frag, in which case refering to them is a no-no.
Only fr_opcode[0,1] are guaranteed to work. */
*buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
*buffer_address
++ = 0xf9;
fragP
->fr_fix
+= 2; /* account for jmp instruction */
subseg_change(SEG_TEXT
,0);
fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
/* only DBcc 68000 instructions can come here */
/* change dbcc into dbcc/jmp absl long */
/* JF: these used to be fr_opcode[2-7], but that's wrong */
*buffer_address
++ = 0x00; /* branch offset = 4 */
*buffer_address
++ = 0x04;
*buffer_address
++ = 0x60; /* put in bra pc+6 */
*buffer_address
++ = 0x06;
*buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
*buffer_address
++ = 0xf9;
fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
subseg_change(SEG_TEXT
,0);
fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
know((fragP
->fr_opcode
[1]&0x40)==0);
fragP
->fr_opcode
[1]|=0x40; /* Turn on LONG bit */
/* The thing to do here is force it to ABSOLUTE LONG, since
PCREL is really trying to shorten an ABSOLUTE address anyway */
/* JF FOO This code has not been tested */
subseg_change(SEG_TEXT
,0);
fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0);
if((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
fragP
->fr_opcode
[0],fragP
->fr_address
);
fragP
->fr_opcode
[1]&= ~0x3F;
fragP
->fr_opcode
[1]|=0x39; /* Mode 7.1 */
/* md_number_to_chars(buffer_address,
(long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
subseg_change(SEG_TEXT
,0);
fix_new(fragP
,(int)(fragP
->fr_fix
),2,fragP
->fr_symbol
,(symbolS
*)0,fragP
->fr_offset
,1);
fragP
->fr_opcode
[1] &= ~0x3F;
fragP
->fr_opcode
[1] |= 0x3A;
subseg_change(SEG_TEXT
,0);
fix_new(fragP
,(int)(fragP
->fr_fix
)+2,4,fragP
->fr_symbol
,(symbolS
*)0,fragP
->fr_offset
+2,1);
*buffer_address
++ = 0x01;
*buffer_address
++ = 0x70;
md_number_to_chars(buffer_address
,(long)disp
,(int)ext
);
/* Force truly undefined symbols to their maximum size, and generally set up
the frag list to be relaxed
md_estimate_size_before_relax(fragP
,segtype
)
register char *buffer_address
= fragP
-> fr_fix
+ fragP
-> fr_literal
;
/* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
switch(fragP
->fr_subtype
) {
case TAB(BRANCH
,SZ_UNDEF
):
if((fragP
->fr_symbol
->sy_type
&N_TYPE
)==segtype
) {
fragP
->fr_subtype
=TAB(TABTYPE(fragP
->fr_subtype
),BYTE
);
} else if(flagseen
['m']) {
if(fragP
->fr_opcode
[0]==0x61) {
fragP
->fr_opcode
[0]= 0x4E;
fragP
->fr_opcode
[1]= 0xB8; /* JBSR with ABSL WORD offset */
subseg_change(SEG_TEXT
, 0);
fix_new(fragP
, fragP
->fr_fix
, 2,
fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0);
fragP
->fr_opcode
[0]= 0x4E;
fragP
->fr_opcode
[1]= 0xB9; /* JBSR with ABSL LONG offset */
subseg_change(SEG_TEXT
, 0);
fix_new(fragP
, fragP
->fr_fix
, 4,
fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0);
} else if(fragP
->fr_opcode
[0]==0x60) {
fragP
->fr_opcode
[0]= 0x4E;
fragP
->fr_opcode
[1]= 0xF8; /* JMP with ABSL WORD offset */
subseg_change(SEG_TEXT
, 0);
fix_new(fragP
, fragP
->fr_fix
, 2,
fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0);
fragP
->fr_opcode
[0]= 0x4E;
fragP
->fr_opcode
[1]= 0xF9; /* JMP with ABSL LONG offset */
subseg_change(SEG_TEXT
, 0);
fix_new(fragP
, fragP
->fr_fix
, 4,
fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0);
as_warn("Long branch offset to extern symbol not supported.");
} else if(flagseen
['l']) { /* Symbol is still undefined. Make it simple */
fix_new(fragP
,(int)(fragP
->fr_fix
),2,fragP
->fr_symbol
,
(symbolS
*)0,fragP
->fr_offset
+ 2,1);
fragP
->fr_opcode
[1]=0x00;
fix_new(fragP
,(int)(fragP
->fr_fix
),4,fragP
->fr_symbol
,
(symbolS
*)0,fragP
->fr_offset
+ 4,1);
fragP
->fr_opcode
[1]=0xff;
case TAB(FBRANCH
,SZ_UNDEF
):
if((fragP
->fr_symbol
->sy_type
&N_TYPE
)==segtype
|| flagseen
['l']) {
fragP
->fr_subtype
=TAB(FBRANCH
,SHORT
);
fragP
->fr_subtype
=TAB(FBRANCH
,LONG
);
case TAB(PCREL
,SZ_UNDEF
):
if((fragP
->fr_symbol
->sy_type
&N_TYPE
)==segtype
|| flagseen
['l']) {
fragP
->fr_subtype
=TAB(PCREL
,SHORT
);
fragP
->fr_subtype
=TAB(PCREL
,LONG
);
case TAB(BCC68000
,SZ_UNDEF
):
if((fragP
->fr_symbol
->sy_type
&N_TYPE
)==segtype
) {
fragP
->fr_subtype
=TAB(BCC68000
,BYTE
);
/* only Bcc 68000 instructions can come here */
/* change bcc into b!cc/jmp absl long */
fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
/* JF: these were fr_opcode[2,3] */
buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
buffer_address
[1] = 0xf8;
fragP
->fr_fix
+= 2; /* account for jmp instruction */
subseg_change(SEG_TEXT
,0);
fix_new(fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, 0,
fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
/* JF: these were fr_opcode[2,3] */
buffer_address
[2] = 0x4e; /* put in jmp long (0x4ef9) */
buffer_address
[3] = 0xf9;
fragP
->fr_fix
+= 2; /* account for jmp instruction */
subseg_change(SEG_TEXT
,0);
fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
if((fragP
->fr_symbol
->sy_type
&N_TYPE
)==segtype
) {
fragP
->fr_subtype
=TAB(DBCC
,SHORT
);
/* only DBcc 68000 instructions can come here */
/* change dbcc into dbcc/jmp absl long */
/* JF: these used to be fr_opcode[2-4], which is wrong. */
buffer_address
[0] = 0x00; /* branch offset = 4 */
buffer_address
[1] = 0x04;
buffer_address
[2] = 0x60; /* put in bra pc + ... */
/* JF: these were fr_opcode[5-7] */
buffer_address
[3] = 0x04; /* plus 4 */
buffer_address
[4] = 0x4e;/* Put in Jump Word */
buffer_address
[5] = 0xf8;
fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
subseg_change(SEG_TEXT
,0);
fix_new(fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, 0,
/* JF: these were fr_opcode[5-7] */
buffer_address
[3] = 0x06; /* Plus 6 */
buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
buffer_address
[5] = 0xf9;
fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
subseg_change(SEG_TEXT
,0);
fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
case TAB(PCLEA
,SZ_UNDEF
):
if((fragP
->fr_symbol
->sy_type
&N_TYPE
)==segtype
|| flagseen
['l']) {
fragP
->fr_subtype
=TAB(PCLEA
,SHORT
);
fragP
->fr_subtype
=TAB(PCLEA
,LONG
);
/* now that SZ_UNDEF are taken care of, check others */
switch(fragP
->fr_subtype
) {
/* We can't do a short jump to the next instruction,
so we force word mode. */
if(fragP
->fr_symbol
&& fragP
->fr_symbol
->sy_value
==0 &&
fragP
->fr_symbol
->sy_frag
==fragP
->fr_next
) {
fragP
->fr_subtype
=TAB(TABTYPE(fragP
->fr_subtype
),SHORT
);
return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
/* the bit-field entries in the relocation_info struct plays hell
with the byte-order problems of cross-assembly. So as a hack,
I added this mach. dependent ri twiddler. Ugly, but it gets
/* on m68k: first 4 bytes are normal unsigned long, next three bytes
are symbolnum, most sig. byte first. Last byte is broken up with
bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
nibble as nuthin. (on Sun 3 at least) */
struct relocation_info
*ri_p
, ri
;
unsigned char the_bytes
[8];
md_number_to_chars(the_bytes
, ri
.r_address
, sizeof(ri
.r_address
));
the_bytes
[4] = (ri
.r_symbolnum
>> 16) & 0x0ff;
the_bytes
[5] = (ri
.r_symbolnum
>> 8) & 0x0ff;
the_bytes
[6] = ri
.r_symbolnum
& 0x0ff;
the_bytes
[7] = (((ri
.r_pcrel
<< 7) & 0x80) | ((ri
.r_length
<< 5) & 0x60) |
((ri
.r_extern
<< 4) & 0x10));
/* now put it back where you found it */
bcopy (the_bytes
, (char *)ri_p
, sizeof(struct relocation_info
));
const int md_short_jump_size
= 4;
const int md_long_jump_size
= 6;
md_create_short_jump(ptr
,from_addr
,to_addr
,frag
,to_symbol
)
offset
= to_addr
- (from_addr
+2);
md_number_to_chars(ptr
,(long)0x6000,2);
md_number_to_chars(ptr
+2,(long)offset
,2);
md_create_long_jump(ptr
,from_addr
,to_addr
,frag
,to_symbol
)
offset
=to_addr
-to_symbol
->sy_value
;
md_number_to_chars(ptr
,(long)0x4EF9,2);
md_number_to_chars(ptr
+2,(long)offset
,4);
fix_new(frag
,(ptr
+2)-frag
->fr_literal
,4,to_symbol
,(symbolS
*)0,(long int)0,0);
offset
=to_addr
- (from_addr
+2);
md_number_to_chars(ptr
,(long)0x60ff,2);
md_number_to_chars(ptr
+2,(long)offset
,4);
/* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
60: absolute -128:127 only
sscanf(exp
->e_beg
+2,"%x",&l
);
sscanf(exp
->e_beg
+1,"%O",&l
);
if(!exp
->e_beg
|| !exp
->e_end
) {
offs(exp
)= (ok
==10) ? 1 : 0;
as_warn("Null expression defaults to %ld",offs(exp
));
if(/* ok!=80 && */exp
->e_end
[-1]==':' && (exp
->e_end
-exp
->e_beg
)>=2) {
as_bad("Unknown size for expression \"%c\"",exp
->e_end
[0]);
save_in
=input_line_pointer
;
input_line_pointer
=exp
->e_beg
;
switch(expression(&(exp
->e_exp
))) {
offs(exp
)= (ok
==10) ? 1 : 0;
as_warn("Unknown expression: '%s' defaulting to %d",exp
->e_beg
,offs(exp
));
/* Do the same thing the VAX asm does */
as_warn("expression out of range: defaulting to 1");
if(offs(exp
)<1 || offs(exp
)>8) {
as_warn("expression out of range: defaulting to 1");
if(offs(exp
)<0 || offs(exp
)>7)
if(offs(exp
)<0 || offs(exp
)>15)
if(offs(exp
)<0 || offs(exp
)>32)
if(offs(exp
)<0 || offs(exp
)>127)
if(offs(exp
)<-64 || offs(exp
)>63)
if(offs(exp
)<-128 || offs(exp
)>127)
if(offs(exp
)<0 || offs(exp
)>4095) {
as_warn("expression out of range: defaulting to 0");
offs(exp
)= (ok
==10) ? 1 : 0;
as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp
->e_beg
,offs(exp
));
if(ok
==80 && offs(exp
)<0) { /* HACK! Turn it into a long */
gen_to_words(words
,2,8L);/* These numbers are magic! */
offs(exp
)=words
[1]|(words
[0]<<16);
offs(exp
)= (ok
==10) ? 1 : 0;
as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp
->e_beg
,offs(exp
));
if(input_line_pointer
!=exp
->e_end
+1)
as_bad("Ignoring junk after expression");
input_line_pointer
=save_in
;
as_warn("expression doesn't fit in BYTE");
as_warn("expression doesn't fit in WORD");
/* These are the back-ends for the various machine dependent pseudo-ops. */
void demand_empty_rest_of_line(); /* Hate those extra verbose names */
demand_empty_rest_of_line();
demand_empty_rest_of_line();
register long int temp_fill
;
temp
= 1; /* JF should be 2? */
temp_fill
= get_absolute_expression ();
if ( ! need_pass_2
) /* Never make frag if expect extra pass. */
frag_align (temp
, (int)temp_fill
);
demand_empty_rest_of_line();
demand_empty_rest_of_line();
/* s_space is defined in read.c .skip is simply an alias to it. */
md_parse_option(argP
,cntP
,vecP
)
case 'l': /* -l means keep external to 2 bit offset
rather than 16 bit one */
/* Gas almost ignores this option! */
if(!strcmp(*argP
,"68000"))
else if(!strcmp(*argP
,"68010")) {
} else if(!strcmp(*argP
,"68020"))
as_warn("Unknown -m option ignored");
/* TEST2: Test md_assemble() */
/* Warning, this routine probably doesn't work anymore */
if(buf
[0]=='|' || buf
[1]=='.')
bzero(&the_ins
,sizeof(the_ins
));
printf("Error %s in %s\n",the_ins
.error
,buf
);
printf("Opcode(%d.%s): ",the_ins
.numo
,the_ins
.args
);
for(n
=0;n
<the_ins
.numo
;n
++)
printf(" 0x%x",the_ins
.opcode
[n
]&0xffff);
print_the_insn(&the_ins
.opcode
[0],stdout
);
for(n
=0;n
<strlen(the_ins
.args
)/2;n
++) {
if(the_ins
.operands
[n
].error
) {
printf("op%d Error %s in %s\n",n
,the_ins
.operands
[n
].error
,buf
);
printf("mode %d, reg %d, ",the_ins
.operands
[n
].mode
,the_ins
.operands
[n
].reg
);
if(the_ins
.operands
[n
].b_const
)
printf("Constant: '%.*s', ",1+the_ins
.operands
[n
].e_const
-the_ins
.operands
[n
].b_const
,the_ins
.operands
[n
].b_const
);
printf("ireg %d, isiz %d, imul %d, ",the_ins
.operands
[n
].ireg
,the_ins
.operands
[n
].isiz
,the_ins
.operands
[n
].imul
);
if(the_ins
.operands
[n
].b_iadd
)
printf("Iadd: '%.*s',",1+the_ins
.operands
[n
].e_iadd
-the_ins
.operands
[n
].b_iadd
,the_ins
.operands
[n
].b_iadd
);
if(str
[-1]==':' || str
[1]=='=')
/* Possible states for relaxation:
0 0 branch offset byte (bra, etc)
1 0 indexed offsets byte a0@(32,d4:w:1) etc
2 0 two-offset index word-word a0@(32,d4)@(45) etc
extern fragS
*text_frag_root
;
for(fragP
=text_frag_root
;fragP
;fragP
=fragP
->fr_next
) {
printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
fragP
->fr_address
,fragP
->fr_next
,fragP
->fr_fix
,fragP
->fr_var
,fragP
->fr_symbol
,fragP
->fr_offset
);
printf("opcode 0x%x type %d subtype %d\n\n",fragP
->fr_opcode
,fragP
->fr_type
,fragP
->fr_subtype
);
fputs("Internal error:",stderr
);
_doprnt(format
,&args
,stderr
);