* Copyright (c) 1982, 1986 Regents of the University of California.
* All rights reserved. The Berkeley software License Agreement
* specifies the terms and conditions for redistribution.
* @(#)if_accreg.h 7.1 (Berkeley) 6/5/86
short csr
; /* control and status */
short db
; /* data buffer */
u_short ba
; /* buss address */
short wc
; /* word count */
* Bits Common to both input and out CSR's
#define ACC_ERR 0x8000 /* error present */
#define ACC_NXM 0x4000 /* non-existant memory */
#define ACC_RDY 0x0080 /* ready */
#define ACC_IE 0x0040 /* interrupt enable */
#define ACC_RESET 0x0002 /* reset interface */
#define ACC_GO 0x0001 /* start operation */
* Input Control Status Register
#define IN_EOM 0x2000 /* end-of-message recieved */
#define IN_HRDY 0x0800 /* host ready */
#define IN_IMPBSY 0x0400 /* IMP not ready */
#define IN_RMR 0x0200 /* receive master ready error */
#define IN_IBF 0x0100 /* input data buffer full */
#define IN_WEN 0x0008 /* write enable */
#define IN_MRDY 0x0004 /* master ready */
"\20\20ERR\17NXM\16EOM\14HRDY\13IMPBSY\12RMR\11IBF\10RDY\7IE\
* Output Control Status Register
#define OUT_TMR 0x0200 /* transmit master ready error */
#define OUT_BBACK 0x0008 /* bus back */
#define OUT_ENLB 0x0004 /* enable last bit */
"\20\20ERR\17NXM\12TMR\10RDY\7IE\4BBACK\3ENLB\2RESET\1GO"