* Copyright (c) 1988 University of Utah.
* Copyright (c) 1992 OMRON Corporation.
* Copyright (c) 1982, 1990, 1992, 1993
* The Regents of the University of California. All rights reserved.
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* %sccs.include.redist.c%
* from: Utah $Hdr: cpu.h 1.16 91/03/25$
* from: hp300/include/cpu.h 7.14 (Berkeley) 5/20/93
* @(#)cpu.h 8.2 (Berkeley) %G%
* Exported definitions unique to luna/68k cpu support,
* definitions of cpu-dependent requirements
* referenced in generic code
#define COPY_SIGCODE /* copy sigcode above user stack in exec */
#define cpu_exec(p) /* nothing */
#define cpu_wait(p) /* nothing */
#define cpu_setstack(p, ap) \
(p)->p_md.md_regs[SP] = ap
* Arguments to hardclock and gatherstats encapsulate the previous
* machine state in an opaque clockframe. One the 68k, we use
* what the hardware pushes on an interrupt (but we pad the sr to a
u_short sr
; /* sr at time of interrupt */
u_long pc
; /* pc at time of interrupt */
u_short vo
; /* vector offset (4-word frame) */
#define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
#define CLKF_PC(framep) ((framep)->pc)
/* We would like to do it this way... */
#define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
/* but until we start using PSL_M, we have to do this instead */
#define CLKF_INTR(framep) (0) /* XXX */
* Preempt the current process if in interrupt from user mode,
* or after the current trap/syscall if in system mode.
#define need_resched() { want_resched++; aston(); }
* Give a profiling tick to the current process when the user profiling
* buffer pages are invalid. On the 68k, request an ast to send us
* through trap, marking the proc as needing a profiling tick.
#define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); }
* Notify the current process (p) that it has a signal pending,
* process as soon as possible.
#define signotify(p) aston()
#define aston() (astpending++)
int astpending
; /* need to trap before returning to user mode */
int want_resched
; /* resched() was called */
* simulated software interrupt register
extern unsigned char ssir
;
#define siroff(x) ssir &= ~(x)
#define setsoftnet() ssir |= SIR_NET
#define setsoftclock() ssir |= SIR_CLOCK
* CTL_MACHDEP definitions.
#define CPU_CONSDEV 1 /* dev_t: console terminal device */
#define CPU_MAXID 2 /* number of valid machdep ids */
#define CTL_MACHDEP_NAMES { \
{ "console_device", CTLTYPE_STRUCT }, \
extern int mmutype
, machineid
;
/* values for machineid */
#define LUNA_I 1 /* 20Mhz 68030 */
#define LUNA_II 2 /* 25Mhz 68040 */
/* values for mmutype (assigned for quick testing) */
#define MMU_68040 -2 /* 68040 on-chip MMU */
#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
/* values for cpuspeed (not really related to clock speed due to caches) */
#define PMMU_LVLMASK 0x0007
#define PMMU_FAULT (PMMU_WP|PMMU_INV)
#define MMU4_CMMASK 0x060
/* 680X0 function codes */
#define FC_USERD 1 /* user data space */
#define FC_USERP 2 /* user program space */
#define FC_PURGE 3 /* HPMMU: clear TLB entries */
#define FC_SUPERD 5 /* supervisor data space */
#define FC_SUPERP 6 /* supervisor program space */
#define FC_CPU 7 /* CPU space */
/* fields in the 68020 cache control register */
#define IC_ENABLE 0x0001 /* enable instruction cache */
#define IC_FREEZE 0x0002 /* freeze instruction cache */
#define IC_CE 0x0004 /* clear instruction cache entry */
#define IC_CLR 0x0008 /* clear entire instruction cache */
/* additional fields in the 68030 cache control register */
#define IC_BE 0x0010 /* instruction burst enable */
#define DC_ENABLE 0x0100 /* data cache enable */
#define DC_FREEZE 0x0200 /* data cache freeze */
#define DC_CE 0x0400 /* clear data cache entry */
#define DC_CLR 0x0800 /* clear entire data cache */
#define DC_BE 0x1000 /* data burst enable */
#define DC_WA 0x2000 /* write allocate */
#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
#define CACHE_OFF (DC_CLR|IC_CLR)
#define CACHE_CLR (CACHE_ON)
#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
/* 68040 cache control register */
#define IC4_ENABLE 0x8000 /* instruction cache enable bit */
#define DC4_ENABLE 0x80000000 /* data cache enable bit */
#define CACHE4_ON (IC4_ENABLE|DC4_ENABLE)