/* ubareg.h 4.22 81/04/03 */
* VAX UNIBUS adapter registers
int uba_cnfgr
; /* configuration register */
int uba_cr
; /* control register */
int uba_sr
; /* status register */
int uba_dcr
; /* diagnostic control register */
int uba_fmer
; /* failed map entry register */
int uba_fubar
; /* failed UNIBUS address register */
int uba_brrvr
[4]; /* receive vector registers */
int uba_dpr
[16]; /* buffered data path register */
struct pte uba_map
[496]; /* unibus map register */
int pad3
[16]; /* no maps for device address space */
#define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */
#define UBACNFGR_UBPDN 0x00020000 /* unibus power down */
#define UBACNFGR_UBIC 0x00010000 /* unibus init complete */
#define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */
#define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */
#define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */
#define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */
#define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */
#define UBACR_IFS 0x00000040 /* interrupt field switch */
#define UBACR_BRIE 0x00000020 /* BR interrupt enable */
#define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */
#define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */
#define UBACR_CNFIE 0x00000004 /* configuration IE */
#define UBACR_UPF 0x00000002 /* UNIBUS power fail */
#define UBACR_ADINIT 0x00000001 /* adapter init */
#define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */
#define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */
#define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */
#define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */
#define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */
#define UBASR_RDS 0x00000200 /* read data substitute */
#define UBASR_CRD 0x00000100 /* corrected read data */
#define UBASR_CXTER 0x00000080 /* command transmit error */
#define UBASR_CXTMO 0x00000040 /* command transmit timeout */
#define UBASR_DPPE 0x00000020 /* data path parity error */
#define UBASR_IVMR 0x00000010 /* invalid map register */
#define UBASR_MRPF 0x00000008 /* map register parity failure */
#define UBASR_LEB 0x00000004 /* lost error */
#define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */
#define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */
"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
#define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */
#define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */
#define UBADPR_BNE 0x80000000 /* buffer not empty - purge */
#define UBADPR_BTE 0x40000000 /* buffer transfer error */
#define UBADPR_DPF 0x20000000 /* DP function (RO) */
#define UBADPR_BS 0x007f0000 /* buffer state field */
#define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */
#define UBADPR_ERROR 0x80000000 /* error occurred */
#define UBADPR_NXM 0x40000000 /* nxm from memory */
#define UBADPR_UCE 0x20000000 /* uncorrectable error */
#define UBADPR_PURGE 0x00000001 /* purge bdp */
#define UBAMR_MRV 0x80000000 /* map register valid */
#define UBAMR_BO 0x02000000 /* byte offset bit */
#define UBAMR_DPDB 0x01e00000 /* data path designator field */
#define UBAMR_SBIPFN 0x000fffff /* SBI page address field */
#define UBAMR_DPSHIFT 21 /* shift to data path designator */
* Number of UNIBUS map registers. We can't use the last 8k of UNIBUS
* address space for i/o transfers since it is used by the devices,
* hence have slightly less than 256K of UNIBUS address space.
* Number of unibus buffered data paths and possible uba's per cpu type.
* Formulas for locations of the last 8k of UNIBUS memory
#define UMEM7ZZ ((u_short *)(0xffe000))
#define UMEM750(i) ((u_short *)(0xffe000-(i)*0x40000))
#define UMEM780(i) ((u_short *)(0x2013e000+(i)*0x40000))