#define DMADDR ((struct device *)(UBA0_DEV+0170500))
int ndh11
; /* Set by dh.c to number of lines */
#define TURNON 03 /* CD lead, line enable */
#define RQS 04 /* request to send */
#define TURNOFF 1 /* line enable only */
* Turn on the line associated with the (DH) device dev.
register struct device
*addr
;
while (addr
->dmcsr
& SCBUSY
)
if (addr
->dmlstat
&CARRIER
)
addr
->dmcsr
= IENABLE
|SCENABL
;
while ((tp
->t_state
&CARR_ON
)==0)
sleep((caddr_t
)&tp
->t_rawq
, TTIPRI
);
* Dump control bits into the DM registers.
register struct device
*addr
;
while (addr
->dmcsr
& SCBUSY
)
addr
->dmcsr
= IENABLE
|SCENABL
;
* Mainly, deal with carrier transitions.
register struct device
*addr
;
if (addr
->dmcsr
&DONE
&& addr
->dmcsr
&CARRTRANS
) {
tp
= &dh11
[(d
<<4)+(addr
->dmcsr
&017)];
wakeup((caddr_t
)&tp
->t_rawq
);
if ((tp
->t_state
&WOPEN
)==0 &&
if (addr
->dmlstat
& CARRIER
) {
} else if ((tp
->t_state
&TTSTOP
) == 0) {
else if ((addr
->dmlstat
&CARRIER
)==0) {
if ((tp
->t_state
&WOPEN
)==0 &&
(tp
->t_local
&LNOHANG
)==0) {
gsignal(tp
->t_pgrp
, SIGHUP
);
gsignal(tp
->t_pgrp
, SIGCONT
);
flushtty(tp
, FREAD
|FWRITE
);
addr
->dmcsr
= IENABLE
|SCENABL
;