/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
Copyright (C) 1991, 1992 Free Software Foundation, Inc.
This definition file is free software; you can redistribute it
and/or modify it under the terms of the GNU General Public
License as published by the Free Software Foundation; either
version 2, or (at your option) any later version.
This definition file is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#define __BITS4 (SI_TYPE_SIZE / 4)
#define __ll_B (1L << (SI_TYPE_SIZE / 2))
#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
#define __ll_highpart(t) ((USItype) (t) / __ll_B)
/* Define auxiliary asm macros.
1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
multiplies two USItype integers MULTIPLER and MULTIPLICAND,
and generates a two-part USItype product in HIGH_PROD and
2) __umulsidi3(a,b) multiplies two USItype integers A and B,
and returns a UDItype product. This is just a variant of umul_ppmm.
3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
denominator) divides a two-word unsigned integer, composed by the
integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and
places the quotient in QUOTIENT and the remainder in REMAINDER.
HIGH_NUMERATOR must be less than DENOMINATOR for correct operation.
If, in addition, the most significant bit of DENOMINATOR must be 1,
then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
denominator). Like udiv_qrnnd but the numbers are signed. The
quotient is rounded towards 0.
5) count_leading_zeros(count, x) counts the number of zero-bits from
the msb to the first non-zero bit. This is the number of steps X
needs to be shifted left to set the msb. Undefined for X == 0.
6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
high_addend_2, low_addend_2) adds two two-word unsigned integers,
composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and
LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and
LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is
7) sub_ddmmss(high_difference, low_difference, high_minuend,
low_minuend, high_subtrahend, low_subtrahend) subtracts two
two-word unsigned integers, composed by HIGH_MINUEND_1 and
LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2
respectively. The result is placed in HIGH_DIFFERENCE and
LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
If any of these macros are left undefined for a particular CPU,
/* The CPUs come in alphabetical order below.
Please add support for more CPUs here, or improve the current support
(E.g. WE32100, i960, IBM360.) */
#if defined (__GNUC__) && !defined (NO_ASM)
/* We sometimes need to clobber "cc" with gcc2, but that would not be
understood by gcc1. Use cpp to avoid major code duplication. */
#else /* __GNUC__ >= 2 */
#define __CLOBBER_CC : "cc"
#define __AND_CLOBBER_CC , "cc"
#endif /* __GNUC__ < 2 */
#if defined (__a29k__) || defined (___AM29K__)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "%r" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
#define umul_ppmm(xh, xl, m0, m1) \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("multiplu %0,%1,%2" \
__asm__ ("multmu %0,%1,%2" \
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("dividu %0,%3,%4" \
#define count_leading_zeros(count, x) \
: "=r" ((USItype)(count)) \
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "%r" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=g" ((USItype)(sh)), \
: "%0" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=g" ((USItype)(sh)), \
#define umul_ppmm(ph, pl, m0, m1) \
__asm__ ("mulx %3,%0,%1" \
: "=g" ((USItype)(ph)), \
: "%0" ((USItype)(m0)), \
#define udiv_qrnnd(q, r, nh, nl, d) \
__asm__ ("divx %4,%0,%1" \
#define count_leading_zeros(count, x) \
__asm__ ("bsch/1 %1,%0" \
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "%rM" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "rM" ((USItype)(ah)), \
#if defined (_PA_RISC1_1)
#define umul_ppmm(w1, w0, u, v) \
struct {USItype __w1, __w0;} __w1w0; \
__asm__ ("xmpyu %1,%2,%0" \
(w1) = __t.__w1w0.__w1; \
(w0) = __t.__w1w0.__w0; \
#if defined (__i386__) || defined (__i486__)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "%0" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
#define umul_ppmm(w1, w0, u, v) \
: "=a" ((USItype)(w0)), \
#define udiv_qrnnd(q, r, n1, n0, d) \
#define count_leading_zeros(count, x) \
: "=r" (__cbtmp) : "rm" ((USItype)(x))); \
(count) = __cbtmp ^ 31; \
/* Make sure these patterns really improve the code before
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
struct {USItype __l, __h;} __i; \
__asm__ ("fiadd.dd %1,%2,%0" \
: "%f" (__a.__ll), "f" (__b.__ll)); \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
struct {USItype __l, __h;} __i; \
__asm__ ("fisub.dd %1,%2,%0" \
: "%f" (__a.__ll), "f" (__b.__ll)); \
#if defined (___IBMR2__) /* IBM RS6000 */
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "%r" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
#define umul_ppmm(xh, xl, m0, m1) \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mul %0,%2,%3" \
: "=r" ((USItype)(xh)), \
(xh) += ((((SItype) __m0 >> 31) & __m1) \
+ (((SItype) __m1 >> 31) & __m0)); \
#define smul_ppmm(xh, xl, m0, m1) \
__asm__ ("mul %0,%2,%3" \
: "=r" ((USItype)(xh)), \
#define sdiv_qrnnd(q, r, nh, nl, d) \
__asm__ ("div %0,%2,%4" \
: "=r" ((USItype)(q)), "=q" ((USItype)(r)) \
: "r" ((USItype)(nh)), "1" ((USItype)(nl)), "r" ((USItype)(d)))
#define UDIV_NEEDS_NORMALIZATION 1
#define count_leading_zeros(count, x) \
: "=r" ((USItype)(count)) \
#if defined (__mc68000__)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=d" ((USItype)(sh)), \
: "%0" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=d" ((USItype)(sh)), \
#if defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
: "=d" ((USItype)(w0)), \
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divu%.l %4,%1:%0" \
#define sdiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divs%.l %4,%1:%0" \
#define count_leading_zeros(count, x) \
__asm__ ("bfffo %1{%b2:%b2},%0" \
: "=d" ((USItype)(count)) \
: "od" ((USItype)(x)), "n" (0))
/* %/ inserts REGISTER_PREFIX. */
#define umul_ppmm(xh, xl, a, b) \
__asm__ ("| Inlined umul_ppmm
: "=g" ((USItype)(xh)), \
: "d0", "d1", "d2", "d3", "d4")
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addu.co %1,%r4,%r5
: "=r" ((USItype)(sh)), \
: "%rJ" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subu.co %1,%r4,%r5
: "=r" ((USItype)(sh)), \
: "rJ" ((USItype)(ah)), \
#define count_leading_zeros(count, x) \
(count) = __cbtmp ^ 31; \
#if defined (__mc88110__)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu.d r10,%2,%3
#define udiv_qrnnd(q, r, n1, n0, d) \
#define umul_ppmm(w1, w0, u, v) \
: "=d" ((USItype)(w0)), \
#if defined (__ns32000__)
#define __umulsidi3(u, v) \
#define div_qrnnd(q, r, n1, n0, d) \
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "%0" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
/* This insn doesn't work on ancient pyramids. */
#define umul_ppmm(w1, w0, u, v) \
struct {USItype __h, __l;} __i; \
#if defined (__ibm032__) /* RT/ROMP */
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "%0" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
#define umul_ppmm(ph, pl, m0, m1) \
USItype __m0 = (m0), __m1 = (m1); \
: "=r" ((USItype)(ph)), \
(ph) += ((((SItype) __m0 >> 31) & __m1) \
+ (((SItype) __m1 >> 31) & __m0)); \
#define count_leading_zeros(count, x) \
: "=r" ((USItype)(count)) \
: "r" ((USItype)(x) >> 16)); \
: "=r" ((USItype)(count)) \
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
: "%r" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=r" ((USItype)(sh)), \
#if defined (__sparc_v8__)
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" \
: "=r" ((USItype)(w1)), \
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
: "=&r" ((USItype)(q)), \
#if defined (__sparclite__)
/* This has hardware multiply but not divide. It also has two additional
instructions scan (ffs from high bit) and divscc. */
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" \
: "=r" ((USItype)(w1)), \
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("! Inlined udiv_qrnnd
wr %%g0,%2,%%y ! Not a delayed write for sparclite
1: ! End of inline udiv_qrnnd" \
: "%g1" __AND_CLOBBER_CC)
#define count_leading_zeros(count, x) \
__asm__ ("scan %1,0,%0" \
: "r" ((USItype)(count)))
/* SPARC without integer multiplication and divide instructions.
(i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("! Inlined umul_ppmm
wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
sra %3,31,%%g2 ! Don't move this insn
and %2,%%g2,%%g2 ! Don't move this insn
andcc %%g0,0,%%g1 ! Don't move this insn
: "=r" ((USItype)(w1)), \
: "%rI" ((USItype)(u)), \
: "%g1", "%g2" __AND_CLOBBER_CC)
#define UMUL_TIME 39 /* 39 instructions */
/* It's quite necessary to add this much assembler for the sparc.
The default udiv_qrnnd (in C) is more than 10 times slower! */
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("! Inlined udiv_qrnnd
addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
sub %1,%2,%1 ! this kills msb of n
addx %1,%1,%1 ! so this can't give carry
addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
sub %1,%2,%1 ! this kills msb of n
! Got carry from n. Subtract next step to cancel this carry.
addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb
! End of inline udiv_qrnnd" \
: "=&r" ((USItype)(q)), \
"0" ((USItype)(n0)) : "%g1" __AND_CLOBBER_CC)
#define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
#endif /* __sparclite__ */
#endif /* __sparc_v8__ */
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
: "=g" ((USItype)(sh)), \
: "%0" ((USItype)(ah)), \
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
: "=g" ((USItype)(sh)), \
#define umul_ppmm(xh, xl, m0, m1) \
struct {USItype __l, __h;} __i; \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("emul %1,%2,$0,%0" \
(xh) += ((((SItype) __m0 >> 31) & __m1) \
+ (((SItype) __m1 >> 31) & __m0)); \
/* If this machine has no inline assembler, use C macros. */
#if !defined (add_ssaaaa)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
(sh) = (ah) + (bh) + (__x < (al)); \
#if !defined (sub_ddmmss)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
(sh) = (ah) - (bh) - (__x > (al)); \
#define umul_ppmm(w1, w0, u, v) \
USItype __x0, __x1, __x2, __x3; \
USItype __ul, __vl, __uh, __vh; \
__ul = __ll_lowpart (u); \
__uh = __ll_highpart (u); \
__vl = __ll_lowpart (v); \
__vh = __ll_highpart (v); \
__x0 = (USItype) __ul * __vl; \
__x1 = (USItype) __ul * __vh; \
__x2 = (USItype) __uh * __vl; \
__x3 = (USItype) __uh * __vh; \
__x1 += __ll_highpart (__x0);/* this can't give carry */ \
__x1 += __x2; /* but this indeed can */ \
if (__x1 < __x2) /* did we get it? */ \
__x3 += __ll_B; /* yes, add it in the proper pos. */ \
(w1) = __x3 + __ll_highpart (__x1); \
(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
#if !defined (__umulsidi3)
#define __umulsidi3(u, v) \
umul_ppmm (__w.s.high, __w.s.low, u, v); \
/* Define this unconditionally, so it can be used for debugging. */
#define __udiv_qrnnd_c(q, r, n1, n0, d) \
USItype __d1, __d0, __q1, __q0; \
USItype __r1, __r0, __m; \
__d1 = __ll_highpart (d); \
__d0 = __ll_lowpart (d); \
__m = (USItype) __q1 * __d0; \
__r1 = __r1 * __ll_B | __ll_highpart (n0); \
if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
__m = (USItype) __q0 * __d0; \
__r0 = __r0 * __ll_B | __ll_lowpart (n0); \
(q) = (USItype) __q1 * __ll_B | __q0; \
/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
__udiv_w_sdiv (defined in libgcc or elsewhere). */
#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
#define udiv_qrnnd(q, r, nh, nl, d) \
(q) = __udiv_w_sdiv (&__r, nh, nl, d); \
/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
#if !defined (udiv_qrnnd)
#define UDIV_NEEDS_NORMALIZATION 1
#define udiv_qrnnd __udiv_qrnnd_c
#if !defined (count_leading_zeros)
extern const UQItype __clz_tab
[];
#define count_leading_zeros(count, x) \
if (SI_TYPE_SIZE <= 32) \
__a = __xr < (1<<2*__BITS4) \
? (__xr < (1<<__BITS4) ? 0 : __BITS4) \
: (__xr < (1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
for (__a = SI_TYPE_SIZE - 8; __a > 0; __a -= 8) \
if (((__xr >> __a) & 0xff) != 0) \
(count) = SI_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
#ifndef UDIV_NEEDS_NORMALIZATION
#define UDIV_NEEDS_NORMALIZATION 0