BSD 4_1_snap development

Work on file sys/h/cpu.h
Work on file sys/h/mem.h
Work on file sys/h/nexus.h
Work on file sys/h/ubareg.h

Synthesized-from: CSRG/cd1/4.1.snap

diff --git a/sys/h/cpu.h b/sys/h/cpu.h
new file mode 100644 (file)
index 0000000..6b9aff7
--- /dev/null
+++ b/sys/h/cpu.h
@@ -0,0 +1,58 @@
+/*     cpu.h   4.6     81/04/03        */
+
+#ifndef LOCORE
+/*
+ * Cpu identification, from SID register.
+ */
+union cpusid {
+       int     cpusid;
+       struct cpuany {
+               u_int   :24,
+                       cp_type:8;
+       } cpuany;
+       struct cpu780 {
+               u_int   cp_sno:12,              /* serial number */
+                       cp_plant:3,             /* plant number */
+                       cp_eco:9,               /* eco level */
+                       cp_type:8;              /* VAX_780 */
+       } cpu780;
+       struct cpu750 {
+               u_int   cp_hrev:8,              /* hardware rev level */
+                       cp_urev:8,              /* ucode rev level */
+                       :8,
+                       cp_type:8;              /* VAX_750 */
+       } cpu750;
+       /* need structure for 7ZZ */
+};
+#endif
+#define        VAX_780         1
+#define        VAX_750         2
+#define        VAX_7ZZ         3
+
+#define        VAX_MAX         3
+
+#ifndef LOCORE
+/*
+ * Per-cpu information for system.
+ */
+struct percpu {
+       short   pc_cputype;             /* cpu type code */
+       short   pc_nnexus;              /* number of nexus slots */
+       struct  nexus *pc_nexbase;      /* base of nexus space */
+/* we should be able to have just one address for the unibus memories */
+/* and calculate successive addresses by adding to the base, but the 750 */
+/* doesn't obey the sensible rule: uba1 has a lower address than uba0! */
+       caddr_t *pc_umaddr;             /* unibus memory addresses */
+       short   pc_nubabdp;             /* number of bdp's per uba */
+       short   pc_haveubasr;           /* have uba status register */
+/* the 750 has some slots which don't promise to tell you their types */
+/* if this pointer is non-zero, then you get the type from this array */
+/* rather than from the (much more sensible) low byte of the config register */
+       short   *pc_nextype;            /* botch */
+};
+
+#ifdef KERNEL
+int    cpu;
+struct percpu percpu[];
+#endif
+#endif

diff --git a/sys/h/mem.h b/sys/h/mem.h
new file mode 100644 (file)
index 0000000..13f0928
--- /dev/null
+++ b/sys/h/mem.h
@@ -0,0 +1,84 @@
+/*     mem.h   4.9     81/04/03        */
+
+/*
+ * Memory controller registers
+ *
+ * The way in which the data is stored in these registers varies
+ * per cpu, so we define macros here to mask that.
+ */
+struct mcr {
+       int     mc_reg[3];
+};
+
+/*
+ * Compute maximum possible number of memory controllers,
+ * for sizing of the mcraddr array.
+ */
+#if VAX780
+#define        MAXNMCR         4
+#else
+#define        MAXNMCR         1
+#endif
+
+/*
+ * For each processor type we define 5 macros:
+ *     M???_INH(mcr)           inhibits further crd interrupts from mcr
+ *     M???_ENA(mcr)           enables another crd interrupt from mcr
+ *     M???_ERR(mcr)           tells whether an error is waiting
+ *     M???_SYN(mcr)           gives the syndrome bits of the error
+ *     M???_ADDR(mcr)          gives the address of the error
+ */
+#if VAX780
+#define        M780_ICRD       0x40000000      /* inhibit crd interrupts, in [2] */
+#define        M780_HIER       0x20000000      /* high error rate, in reg[2] */
+#define        M780_ERLOG      0x10000000      /* error log request, in reg[2] */
+/* on a 780, memory crd's occur only when bit 15 is set in the SBIER */
+/* register; bit 14 there is an error bit which we also clear */
+/* these bits are in the back of the ``red book'' (or in the VMS code) */
+
+#define        M780_INH(mcr)   \
+       (((mcr)->mc_reg[2] = (M780_ICRD|M780_HIER|M780_ERLOG)), mtpr(SBIER, 0))
+#define        M780_ENA(mcr)   \
+       (((mcr)->mc_reg[2] = (M780_HIER|M780_ERLOG)), mtpr(SBIER, 3<<14))
+#define        M780_ERR(mcr)   \
+       ((mcr)->mc_reg[2] & (M780_ERLOG))
+
+#define        M780_SYN(mcr)   ((mcr)->mc_reg[2] & 0xff)
+#define        M780_ADDR(mcr)  (((mcr)->mc_reg[2] >> 8) & 0xfffff)
+#endif
+
+#if VAX750
+#define        M750_ICRD       0x10000000      /* inhibit crd interrupts, in [1] */
+#define        M750_UNCORR     0xc0000000      /* uncorrectable error, in [0] */
+#define        M750_CORERR     0x40000000      /* correctable error, in [0] */
+
+#define        M750_INH(mcr)   ((mcr)->mc_reg[1] = M750_ICRD)
+#define        M750_ENA(mcr)   ((mcr)->mc_reg[0] = (M750_UNCORR|M750_CORERR), \
+                           (mcr)->mc_reg[1] = 0)
+#define        M750_ERR(mcr)   ((mcr)->mc_reg[0] & (M750_UNCORR|M750_CORERR))
+
+#define        M750_SYN(mcr)   ((mcr)->mc_reg[0] & 0x3f)
+#define        M750_ADDR(mcr)  (((mcr)->mc_reg[0] >> 8) & 0x7fff)
+#endif
+
+#if VAX7ZZ
+#define        M7ZZ_CRD        0x40000000      /* crd, in [1] */
+#define        M7ZZ_FTBPE      0x20000000      /* force tbuf parity error, in [1] */
+#define        M7ZZ_ENACRD     0x10000000      /* enable crd interrupt, in [1] */
+#define        M7ZZ_MME        0x08000000      /* mem-man enable (ala ipr), in [1] */
+#define        M7ZZ_DM         0x04000000      /* diagnostic mode, in [1] */
+#define        M7ZZ_DISECC     0x02000000      /* disable ecc, in [1] */
+
+#define        M7ZZ_INH(mcr)   ((mcr)->mc_reg[1] = M7ZZ_MME)
+#define        M7ZZ_ENA(mcr)   ((mcr)->mc_reg[1] = (M7ZZ_MME|M7ZZ_ENACRD))
+#define        M7ZZ_ERR(mcr)   ((mcr)->mc_reg[1] & M7ZZ_CRD)
+#define        M7ZZ_SYN(mcr)   ((mcr)->mc_reg[0] & 0x7f)
+#define        M7ZZ_ADDR(mcr)  (((mcr)->mc_reg[0] >> 8) & 0x7fff)
+#endif
+
+#define        MEMINTVL        (60*60*10)              /* 10 minutes */
+
+#ifdef KERNEL
+int    nmcr;
+struct mcr *mcraddr[MAXNMCR];
+#endif

diff --git a/sys/h/nexus.h b/sys/h/nexus.h
new file mode 100644 (file)
index 0000000..18dbfaf
--- /dev/null
+++ b/sys/h/nexus.h
@@ -0,0 +1,86 @@
+/*     nexus.h 4.10    81/04/03        */
+
+/*
+ * Information about nexus's.
+ *
+ * Each machine has an address of backplane slots (nexi).
+ * Each nexus is some type of adapter, whose code is the low
+ * byte of the first word of the adapter address space.
+ * At boot time the system looks through the array of available
+ * slots and finds the interconnects for the machine.
+ */
+#if VAX780
+#define        NNEX780 16
+#define        NEX780  ((struct nexus *)0x20000000)
+#endif
+#if VAX750
+#define        NNEX750 16
+#define        NEX750  ((struct nexus *)0xf20000)
+#endif
+#if VAX7ZZ
+#define        NNEX7ZZ 16
+#define        NEX7ZZ  ((struct nexus *)0xf20000)
+#endif
+#define        NEXSIZE 0x2000
+
+#define        MAXNNEXUS 16
+
+#ifndef LOCORE
+struct nexus {
+       union nexcsr {
+               long    nex_csr;
+               u_char  nex_type;
+       } nexcsr;
+       long    nex_pad[NEXSIZE / sizeof (long) - 1];
+};
+#ifdef KERNEL
+struct nexus nexus[MAXNNEXUS];
+#endif
+#endif
+
+/*
+ * Bits in high word of nexus's.
+ */
+#define        SBI_PARFLT      (1<<31)         /* sbi parity fault */
+#define        SBI_WSQFLT      (1<<30)         /* write sequence fault */
+#define        SBI_URDFLT      (1<<29)         /* unexpected read data fault */
+#define        SBI_ISQFLT      (1<<28)         /* interlock sequence fault */
+#define        SBI_MXTFLT      (1<<27)         /* multiple transmitter fault */
+#define        SBI_XMTFLT      (1<<26)         /* transmit fault */
+
+#define        NEX_CFGFLT      (0xfc000000)
+
+#ifndef LOCORE
+#if VAX780
+#define        NEXFLT_BITS \
+"\20\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT"
+#endif
+#endif
+
+#define        NEX_APD         (1<<23)         /* adaptor power down */
+#define        NEX_APU         (1<<22)         /* adaptor power up */
+
+#define        MBA_OT          (1<<21)         /* overtemperature */
+
+#define        UBA_UBINIT      (1<<18)         /* unibus init */
+#define        UBA_UBPDN       (1<<17)         /* unibus power down */
+#define        UBA_UBIC        (1<<16)         /* unibus initialization complete */
+
+/*
+ * Types for nex_type.
+ */
+#define        NEX_ANY         0               /* pseudo for handling 11/750 */
+#define        NEX_MEM4        0x08            /* 4K chips, non-interleaved mem */
+#define        NEX_MEM4I       0x09            /* 4K chips, interleaved mem */
+#define        NEX_MEM16       0x10            /* 16K chips, non-interleaved mem */
+#define        NEX_MEM16I      0x11            /* 16K chips, interleaved mem */
+#define        NEX_MBA         0x20            /* Massbus adaptor */
+#define        NEX_UBA0        0x28            /* Unibus adaptor */
+#define        NEX_UBA1        0x29            /* 4 flavours for 4 addr spaces */
+#define        NEX_UBA2        0x2a
+#define        NEX_UBA3        0x2b
+#define        NEX_DR32        0x30            /* DR32 user i'face to SBI */
+#define        NEX_MPM0        0x40            /* Multi-port mem */
+#define        NEX_MPM1        0x41            /* Who knows why 4 different ones ? */
+#define        NEX_MPM2        0x42
+#define        NEX_MPM3        0x43

diff --git a/sys/h/ubareg.h b/sys/h/ubareg.h
new file mode 100644 (file)
index 0000000..ab28c7b
--- /dev/null
+++ b/sys/h/ubareg.h
@@ -0,0 +1,132 @@
+/*     ubareg.h        4.22    81/04/03        */
+
+/*
+ * VAX UNIBUS adapter registers
+ */
+#ifndef LOCORE
+/*
+ * UBA hardware registers
+ */
+struct uba_regs
+{
+       int     uba_cnfgr;              /* configuration register */
+       int     uba_cr;                 /* control register */
+       int     uba_sr;                 /* status register */
+       int     uba_dcr;                /* diagnostic control register */
+       int     uba_fmer;               /* failed map entry register */
+       int     uba_fubar;              /* failed UNIBUS address register */
+       int     pad1[2];
+       int     uba_brsvr[4];
+       int     uba_brrvr[4];           /* receive vector registers */
+       int     uba_dpr[16];            /* buffered data path register */
+       int     pad2[480];
+       struct  pte uba_map[496];       /* unibus map register */
+       int     pad3[16];               /* no maps for device address space */
+};
+#endif
+
+#if VAX780
+/* uba_cnfgr */
+#define        UBACNFGR_UBINIT 0x00040000      /* unibus init asserted */
+#define        UBACNFGR_UBPDN  0x00020000      /* unibus power down */
+#define        UBACNFGR_UBIC   0x00010000      /* unibus init complete */
+
+/* uba_cr */
+#define        UBACR_MRD16     0x40000000      /* map reg disable bit 4 */
+#define        UBACR_MRD8      0x20000000      /* map reg disable bit 3 */
+#define        UBACR_MRD4      0x10000000      /* map reg disable bit 2 */
+#define        UBACR_MRD2      0x08000000      /* map reg disable bit 1 */
+#define        UBACR_MRD1      0x04000000      /* map reg disable bit 0 */
+#define        UBACR_IFS       0x00000040      /* interrupt field switch */
+#define        UBACR_BRIE      0x00000020      /* BR interrupt enable */
+#define        UBACR_USEFIE    0x00000010      /* UNIBUS to SBI error field IE */
+#define        UBACR_SUEFIE    0x00000008      /* SBI to UNIBUS error field IE */
+#define        UBACR_CNFIE     0x00000004      /* configuration IE */
+#define        UBACR_UPF       0x00000002      /* UNIBUS power fail */
+#define        UBACR_ADINIT    0x00000001      /* adapter init */
+
+/* uba_sr */
+#define        UBASR_BR7FULL   0x08000000      /* BR7 receive vector reg full */
+#define        UBASR_BR6FULL   0x04000000      /* BR6 receive vector reg full */
+#define        UBASR_BR5FULL   0x02000000      /* BR5 receive vector reg full */
+#define        UBASR_BR4FULL   0x01000000      /* BR4 receive vector reg full */
+#define        UBASR_RDTO      0x00000400      /* UNIBUS to SBI read data timeout */
+#define        UBASR_RDS       0x00000200      /* read data substitute */
+#define        UBASR_CRD       0x00000100      /* corrected read data */
+#define        UBASR_CXTER     0x00000080      /* command transmit error */
+#define        UBASR_CXTMO     0x00000040      /* command transmit timeout */
+#define        UBASR_DPPE      0x00000020      /* data path parity error */
+#define        UBASR_IVMR      0x00000010      /* invalid map register */
+#define        UBASR_MRPF      0x00000008      /* map register parity failure */
+#define        UBASR_LEB       0x00000004      /* lost error */
+#define        UBASR_UBSTO     0x00000002      /* UNIBUS select timeout */
+#define        UBASR_UBSSYNTO  0x00000001      /* UNIBUS slave sync timeout */
+
+#define        UBASR_BITS \
+"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
+
+/* uba_brrvr[] */
+#define        UBABRRVR_AIRI   0x80000000      /* adapter interrupt request */
+#define        UBABRRVR_DIV    0x0000ffff      /* device interrupt vector field */
+#endif VAX780
+ 
+/* uba_dpr */
+#if VAX780
+#define        UBADPR_BNE      0x80000000      /* buffer not empty - purge */
+#define        UBADPR_BTE      0x40000000      /* buffer transfer error */
+#define        UBADPR_DPF      0x20000000      /* DP function (RO) */
+#define        UBADPR_BS       0x007f0000      /* buffer state field */
+#define        UBADPR_BUBA     0x0000ffff      /* buffered UNIBUS address */
+#endif VAX780
+#if VAX750
+#define        UBADPR_ERROR    0x80000000      /* error occurred */
+#define        UBADPR_NXM      0x40000000      /* nxm from memory */
+#define        UBADPR_UCE      0x20000000      /* uncorrectable error */
+#define        UBADPR_PURGE    0x00000001      /* purge bdp */
+#endif VAX750
+ 
+/* uba_mr[] */
+#define        UBAMR_MRV       0x80000000      /* map register valid */
+#define        UBAMR_BO        0x02000000      /* byte offset bit */
+#define        UBAMR_DPDB      0x01e00000      /* data path designator field */
+#define        UBAMR_SBIPFN    0x000fffff      /* SBI page address field */
+
+#define        UBAMR_DPSHIFT   21              /* shift to data path designator */
+
+/*
+ * Number of UNIBUS map registers.  We can't use the last 8k of UNIBUS
+ * address space for i/o transfers since it is used by the devices,
+ * hence have slightly less than 256K of UNIBUS address space.
+ */
+#define        NUBMREG 496
+
+/*
+ * Number of unibus buffered data paths and possible uba's per cpu type.
+ */
+#define        NBDP780 15
+#define        NBDP750 3
+#define        NBDP7ZZ 0
+#define        MAXNBDP 15
+
+#define        NUBA780 4
+#define        NUBA750 1
+#define        NUBA7ZZ 1
+#if VAX780
+#define        MAXNUBA 4
+#else
+#define        MAXNUBA 1
+#endif
+
+/*
+ * Formulas for locations of the last 8k of UNIBUS memory
+ * for each possible uba.
+ */
+#if VAX7ZZ
+#define        UMEM7ZZ         ((u_short *)(0xffe000))
+#endif
+#if VAX750
+#define        UMEM750(i)      ((u_short *)(0xffe000-(i)*0x40000))
+#endif
+#if VAX780
+#define        UMEM780(i)      ((u_short *)(0x2013e000+(i)*0x40000))
+#endif