-#define MMU_UMEN 0x0001 /* enable user mapping */
-#define MMU_SMEN 0x0002 /* enable supervisor mapping */
-#define MMU_CEN 0x0004 /* enable data cache */
-#define MMU_BERR 0x0008 /* bus error */
-#define MMU_IEN 0x0020 /* enable instruction cache */
-#define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */
-#define MMU_WPF 0x2000 /* write protect fault */
-#define MMU_PF 0x4000 /* page fault */
-#define MMU_PTF 0x8000 /* page table fault */
-
-#define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR)
-#define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE)
-
-#define PMMU_LVLMASK 0x0007
-#define PMMU_INV 0x0400
-#define PMMU_WP 0x0800
-#define PMMU_ALV 0x1000
-#define PMMU_SO 0x2000
-#define PMMU_LV 0x4000
-#define PMMU_BE 0x8000
-
-#define PMMU_FAULT (PMMU_WP|PMMU_INV)
-
-/* function code for user data space */
-#define FC_USERD 1
-/* methinks the following is used to selectively clear TLB entries */
-#define FC_PURGE 3
+#define MMU_UMEN 0x0001 /* enable user mapping */
+#define MMU_SMEN 0x0002 /* enable supervisor mapping */
+#define MMU_CEN 0x0004 /* enable data cache */
+#define MMU_BERR 0x0008 /* bus error */
+#define MMU_IEN 0x0020 /* enable instruction cache */
+#define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */
+#define MMU_WPF 0x2000 /* write protect fault */
+#define MMU_PF 0x4000 /* page fault */
+#define MMU_PTF 0x8000 /* page table fault */
+
+#define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR)
+#define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE)
+
+#define PMMU_LVLMASK 0x0007
+#define PMMU_INV 0x0400
+#define PMMU_WP 0x0800
+#define PMMU_ALV 0x1000
+#define PMMU_SO 0x2000
+#define PMMU_LV 0x4000
+#define PMMU_BE 0x8000
+
+#define PMMU_FAULT (PMMU_WP|PMMU_INV)
+
+/* 680X0 function codes */
+#define FC_USERD 1 /* user data space */
+#define FC_USERP 2 /* user program space */
+#define FC_PURGE 3 /* HPMMU: clear TLB entries */
+#define FC_SUPERD 5 /* supervisor data space */
+#define FC_SUPERP 6 /* supervisor program space */
+#define FC_CPU 7 /* CPU space */