date and time created 92/07/13 00:44:07 by torek

SCCS-vsn: sys/sparc/sbus/if_lereg.h 7.1
SCCS-vsn: sys/sparc/sbus/sbus.c 7.1
SCCS-vsn: sys/sparc/sbus/sbusreg.h 7.1

diff --git a/usr/src/sys/sparc/sbus/if_lereg.h b/usr/src/sys/sparc/sbus/if_lereg.h
new file mode 100644 (file)
index 0000000..7a025ac
--- /dev/null
+++ b/usr/src/sys/sparc/sbus/if_lereg.h
@@ -0,0 +1,139 @@
+/*-
+ * Copyright (c) 1982, 1992 Regents of the University of California.
+ * All rights reserved.
+ *
+ * %sccs.include.redist.c%
+ *
+ *     @(#)if_lereg.h  7.1 (Berkeley) %G%
+ *
+ * from: $Header: if_lereg.h,v 1.5 92/07/10 06:45:26 torek Exp $
+ */
+
+#define        LEMTU           1518
+#define        LEMINSIZE       60      /* should be 64 if mode DTCR is set */
+#define        LERBUF          8
+#define        LERBUFLOG2      3
+#define        LE_RLEN         (LERBUFLOG2 << 13)
+#define        LETBUF          1
+#define        LETBUFLOG2      0
+#define        LE_TLEN         (LETBUFLOG2 << 13)
+
+/* Local Area Network Controller for Ethernet (LANCE) registers */
+struct lereg1 {
+       u_short ler1_rdp;       /* register data port */
+       u_short ler1_rap;       /* register address port */
+};
+
+/* register addresses */
+#define        LE_CSR0         0               /* Control and status register */
+#define        LE_CSR1         1               /* low address of init block */
+#define        LE_CSR2         2               /* high address of init block */
+#define        LE_CSR3         3               /* Bus master and control */
+
+/* Control and status register 0 (csr0) */
+#define        LE_C0_ERR       0x8000          /* error summary */
+#define        LE_C0_BABL      0x4000          /* transmitter timeout error */
+#define        LE_C0_CERR      0x2000          /* collision */
+#define        LE_C0_MISS      0x1000          /* missed a packet */
+#define        LE_C0_MERR      0x0800          /* memory error */
+#define        LE_C0_RINT      0x0400          /* receiver interrupt */
+#define        LE_C0_TINT      0x0200          /* transmitter interrupt */
+#define        LE_C0_IDON      0x0100          /* initalization done */
+#define        LE_C0_INTR      0x0080          /* interrupt condition */
+#define        LE_C0_INEA      0x0040          /* interrupt enable */
+#define        LE_C0_RXON      0x0020          /* receiver on */
+#define        LE_C0_TXON      0x0010          /* transmitter on */
+#define        LE_C0_TDMD      0x0008          /* transmit demand */
+#define        LE_C0_STOP      0x0004          /* disable all external activity */
+#define        LE_C0_STRT      0x0002          /* enable external activity */
+#define        LE_C0_INIT      0x0001          /* begin initalization */
+
+#define LE_C0_BITS \
+    "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\
+\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
+
+/* Control and status register 3 (csr3) */
+#define        LE_C3_BSWP      0x4             /* byte swap */
+#define        LE_C3_ACON      0x2             /* ALE control, eh? */
+#define        LE_C3_BCON      0x1             /* byte control */
+/*
+ * Current size is 13,758 bytes with 8 x 1518 receive buffers and
+ * 1 x 1518 transmit buffer.
+ */
+struct lereg2 {
+       /* initialization block */
+       u_short ler2_mode;              /* +0x0000: mode */
+       u_char  ler2_padr[6];           /* +0x0002: physical address */
+       u_long  ler2_ladrf[2];          /* +0x0008: logical address filter */
+       u_short ler2_rdra;              /* +0x0010: receive descriptor addr */
+       u_short ler2_rlen;              /* +0x0012: rda high and ring size */
+       u_short ler2_tdra;              /* +0x0014: transmit descriptor addr */
+       u_short ler2_tlen;              /* +0x0016: tda high and ring size */
+       /* receive message descriptors. bits/hadr are byte order dependent. */
+       struct  lermd {                 /* +0x0018 */
+               u_short rmd0;           /* low address of packet */
+               u_char  rmd1_bits;      /* descriptor bits */
+               u_char  rmd1_hadr;      /* high address of packet */
+               short   rmd2;           /* buffer byte count */
+               u_short rmd3;           /* message byte count */
+       } ler2_rmd[LERBUF];
+       /* transmit message descriptors */
+       struct  letmd {                 /* +0x0058 */
+               u_short tmd0;           /* low address of packet */
+               u_char  tmd1_bits;      /* descriptor bits */
+               u_char  tmd1_hadr;      /* high address of packet */
+               short   tmd2;           /* buffer byte count */
+               u_short tmd3;           /* transmit error bits */
+       } ler2_tmd[LETBUF];
+       char    ler2_rbuf[LERBUF][LEMTU]; /* +0x0060 */
+       char    ler2_tbuf[LETBUF][LEMTU]; /* +0x2fd0 */
+};
+
+/* Initialzation block (mode) */
+#define        LE_MODE_PROM    0x8000          /* promiscuous mode */
+/*                     0x7f80             reserved, must be zero */
+#define        LE_MODE_INTL    0x0040          /* internal loopback */
+#define        LE_MODE_DRTY    0x0020          /* disable retry */
+#define        LE_MODE_COLL    0x0010          /* force a collision */
+#define        LE_MODE_DTCR    0x0008          /* disable transmit CRC */
+#define        LE_MODE_LOOP    0x0004          /* loopback mode */
+#define        LE_MODE_DTX     0x0002          /* disable transmitter */
+#define        LE_MODE_DRX     0x0001          /* disable receiver */
+#define        LE_MODE_NORMAL  0               /* none of the above */
+
+
+/* Receive message descriptor 1 (rmd1_bits) */ 
+#define        LE_R1_OWN       0x80            /* LANCE owns the packet */
+#define        LE_R1_ERR       0x40            /* error summary */
+#define        LE_R1_FRAM      0x20            /* framing error */
+#define        LE_R1_OFLO      0x10            /* overflow error */
+#define        LE_R1_CRC       0x08            /* CRC error */
+#define        LE_R1_BUFF      0x04            /* buffer error */
+#define        LE_R1_STP       0x02            /* start of packet */
+#define        LE_R1_ENP       0x01            /* end of packet */
+
+#define LE_R1_BITS \
+    "\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
+
+/* Transmit message descriptor 1 (tmd1_bits) */ 
+#define        LE_T1_OWN       0x80            /* LANCE owns the packet */
+#define        LE_T1_ERR       0x40            /* error summary */
+#define        LE_T1_MORE      0x10            /* multiple collisions */
+#define        LE_T1_ONE       0x08            /* single collision */
+#define        LE_T1_DEF       0x04            /* defferred transmit */
+#define        LE_T1_STP       0x02            /* start of packet */
+#define        LE_T1_ENP       0x01            /* end of packet */
+
+#define LE_T1_BITS \
+    "\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
+
+/* Transmit message descriptor 3 (tmd3) */ 
+#define        LE_T3_BUFF      0x8000          /* buffer error */
+#define        LE_T3_UFLO      0x4000          /* underflow error */
+#define        LE_T3_LCOL      0x1000          /* late collision */
+#define        LE_T3_LCAR      0x0800          /* loss of carrier */
+#define        LE_T3_RTRY      0x0400          /* retry error */
+#define        LE_T3_TDR_MASK  0x03ff          /* time domain reflectometry counter */
+
+#define LE_T3_BITS \
+    "\20\20BUFF\17UFLO\16RES\15LCOL\14LCAR\13RTRY"

diff --git a/usr/src/sys/sparc/sbus/sbus.c b/usr/src/sys/sparc/sbus/sbus.c
new file mode 100644 (file)
index 0000000..539cbfb
--- /dev/null
+++ b/usr/src/sys/sparc/sbus/sbus.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 1992 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * %sccs.include.redist.c%
+ *
+ *     @(#)sbus.c      7.1 (Berkeley) %G%
+ *
+ * from: $Header: sbus.c,v 1.8 92/06/17 06:59:43 torek Exp $ (LBL)
+ */
+
+/*
+ * Sbus stuff.
+ */
+
+/* #include "sbus.h" */
+#define NSBUS 1        /* XXX */
+
+#include "sys/param.h"
+#include "sys/device.h"
+
+#include "machine/autoconf.h"
+
+#include "sbusreg.h"
+#include "sbusvar.h"
+
+/* autoconfiguration driver */
+void   sbus_attach __P((struct device *, struct device *, void *));
+struct cfdriver sbuscd =
+    { NULL, "sbus", matchbyname, sbus_attach,
+      DV_DULL, sizeof(struct sbus_softc) };
+
+/*
+ * Print the location of some sbus-attached device (called just
+ * before attaching that device).  If `sbus' is not NULL, the
+ * device was found but not configured; print the sbus as well.
+ * Return UNCONF (config_find ignores this if the device was configured).
+ */
+int
+sbus_print(args, sbus)
+       void *args;
+       char *sbus;
+{
+       register struct sbus_attach_args *sa = args;
+
+       if (sbus)
+               printf("%s at %s", sa->sa_ra.ra_name, sbus);
+       printf(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset);
+       return (UNCONF);
+}
+
+/*
+ * Attach an Sbus.
+ */
+void
+sbus_attach(parent, self, aux)
+       struct device *parent;
+       struct device *self;
+       void *aux;
+{
+       register struct sbus_softc *sc = (struct sbus_softc *)self;
+       register int base, node, slot;
+       register char *name;
+       struct sbus_attach_args sa;
+
+       /*
+        * XXX there is only one Sbus, for now -- do not know how to
+        * address children on others
+        */
+       if (sc->sc_dev.dv_unit > 0) {
+               printf(" unsupported\n");
+               return;
+       }
+
+       /*
+        * Record clock frequency for synchronous SCSI.
+        * IS THIS THE CORRECT DEFAULT??
+        */
+       node = ((struct romaux *)aux)->ra_node;
+       sc->sc_clockfreq = getpropint(node, "clock-frequency", 25*1000*1000);
+       printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq));
+
+       /*
+        * Loop through ROM children, fixing any relative addresses
+        * and then configuring each device.
+        */
+       for (node = firstchild(node); node; node = nextsibling(node)) {
+               name = getpropstring(node, "name");
+               if (!romprop(&sa.sa_ra, name, node))
+                       continue;
+               base = (int)sa.sa_ra.ra_paddr;
+               if (SBUS_ABS(base)) {
+                       sa.sa_slot = SBUS_ABS_TO_SLOT(base);
+                       sa.sa_offset = SBUS_ABS_TO_OFFSET(base);
+               } else {
+                       sa.sa_slot = slot = sa.sa_ra.ra_iospace;
+                       sa.sa_offset = base;
+                       sa.sa_ra.ra_paddr = (void *)SBUS_ADDR(slot, base);
+               }
+               (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print);
+       }
+}
+
+/*
+ * Each attached device calls sbus_establish after it initializes
+ * its sbusdev portion.
+ */
+void
+sbus_establish(sd, dev)
+       register struct sbusdev *sd;
+       register struct device *dev;
+{
+       register struct sbus_softc *sc = (struct sbus_softc *)dev->dv_parent;
+
+       sd->sd_dev = dev;
+       sd->sd_bchain = sc->sc_sbdev;
+       sc->sc_sbdev = sd;
+}
+
+/*
+ * Reset the given sbus. (???)
+ */
+void
+sbusreset(sbus)
+       int sbus;
+{
+       register struct sbusdev *sd;
+       struct sbus_softc *sc = sbuscd.cd_devs[sbus];
+       struct device *dev;
+
+       printf("reset %s:", sc->sc_dev.dv_xname);
+       for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) {
+               if (sd->sd_reset) {
+                       dev = sd->sd_dev;
+                       (*sd->sd_reset)(dev);
+                       printf(" %s", dev->dv_xname);
+               }
+       }
+}

diff --git a/usr/src/sys/sparc/sbus/sbusreg.h b/usr/src/sys/sparc/sbus/sbusreg.h
new file mode 100644 (file)
index 0000000..ba39ea7
--- /dev/null
+++ b/usr/src/sys/sparc/sbus/sbusreg.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 1992 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * %sccs.include.redist.c%
+ *
+ *     @(#)sbusreg.h   7.1 (Berkeley) %G%
+ *
+ * from: $Header: sbusreg.h,v 1.5 92/06/17 06:59:44 torek Exp $ (LBL)
+ */
+
+/*
+ * Sun-4c S-bus definitions.  (Should be made generic!)
+ *
+ * Sbus slot 0 is not a separate slot; it talks to the onboard I/O devices.
+ * It is, however, addressed just like any `real' Sbus.
+ *
+ * Sbus device addresses are obtained from the FORTH PROMs.  They come
+ * in `absolute' and `relative' address flavors, so we have to handle both.
+ * Relative addresses do *not* include the slot number.
+ */
+#define        SBUS_BASE               0xf8000000
+#define        SBUS_ADDR(slot, off)    (SBUS_BASE + ((slot) << 25) + (off))
+#define        SBUS_ABS(a)             ((unsigned)(a) >= SBUS_BASE)
+#define        SBUS_ABS_TO_SLOT(a)     (((a) - SBUS_BASE) >> 25)
+#define        SBUS_ABS_TO_OFFSET(a)   (((a) - SBUS_BASE) & 0x1ffffff)