branches because addl and shll set the N bit differently; outside of this
situation, turn more shll's into addl's.
SCCS-vsn: old/pcc/c2.tahoe/c21.c 1.10
-static char sccsid[] = "@(#)c21.c 1.9 (Berkeley/CCI) %G%";
+static char sccsid[] = "@(#)c21.c 1.10 (Berkeley/CCI) %G%";
}
pf->pop = 0;
redunm++; nsaddr++;
}
pf->pop = 0;
redunm++; nsaddr++;
ashadd:
/* at this point, RT2 and RT3 are guaranteed to be simple regs*/
if (shcnt == 1) {
ashadd:
/* at this point, RT2 and RT3 are guaranteed to be simple regs*/
if (shcnt == 1) {
** shll $1,A,A > addl2 A,A
** shll $1,A,B > addl3 A,A,B
*/
** shll $1,A,A > addl2 A,A
** shll $1,A,B > addl3 A,A,B
*/
+ if ((pf = p->forw)->op == CBR ||
+ (pf->op == MOV && (pf = pf->forw)->op == CBR))
+ /*
+ ** shll and addl handle the N bit differently
+ ** on overflow; avoid N bit CBRs
+ */
+ switch (pf->subop) {
+ case JLE: case JGE: case JLT: case JGT:
+ goto std;
+ }
p->op = ADD;
strcpy(regs[RT1], regs[RT2]);
if(equstr(regs[RT2], regs[RT3])) {
p->op = ADD;
strcpy(regs[RT1], regs[RT2]);
if(equstr(regs[RT2], regs[RT3])) {