date and time created 92/07/13 00:42:16 by torek

SCCS-vsn: sys/sparc/fpu/fpu_add.c 7.1
SCCS-vsn: sys/sparc/fpu/fpu_arith.h 7.1

diff --git a/usr/src/sys/sparc/fpu/fpu_add.c b/usr/src/sys/sparc/fpu/fpu_add.c
new file mode 100644 (file)
index 0000000..35641f5
--- /dev/null
+++ b/usr/src/sys/sparc/fpu/fpu_add.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 1992 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * %sccs.include.redist.c%
+ *
+ *     @(#)fpu_add.c   7.1 (Berkeley) %G%
+ *
+ * from: $Header: fpu_add.c,v 1.3 92/06/17 18:11:43 mccanne Exp $
+ */
+
+/*
+ * Perform an FPU add (return x + y).
+ *
+ * To subtract, negate y and call add.
+ */
+
+#include "sys/types.h"
+
+#include "machine/reg.h"
+
+#include "fpu_arith.h"
+#include "fpu_emu.h"
+
+struct fpn *
+fpu_add(fe)
+       register struct fpemu *fe;
+{
+       register struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2, *r;
+       register u_int r0, r1, r2, r3;
+       register int rd;
+
+       /*
+        * Put the `heavier' operand on the right (see fpu_emu.h).
+        * Then we will have one of the following cases, taken in the
+        * following order:
+        *
+        *  - y = NaN.  Implied: if only one is a signalling NaN, y is.
+        *      The result is y.
+        *  - y = Inf.  Implied: x != NaN (is 0, number, or Inf: the NaN
+        *    case was taken care of earlier).
+        *      If x = -y, the result is NaN.  Otherwise the result
+        *      is y (an Inf of whichever sign).
+        *  - y is 0.  Implied: x = 0.
+        *      If x and y differ in sign (one positive, one negative),
+        *      the result is +0 except when rounding to -Inf.  If same:
+        *      +0 + +0 = +0; -0 + -0 = -0.
+        *  - x is 0.  Implied: y != 0.
+        *      Result is y.
+        *  - other.  Implied: both x and y are numbers.
+        *      Do addition a la Hennessey & Patterson.
+        */
+       ORDER(x, y);
+       if (ISNAN(y))
+               return (y);
+       if (ISINF(y)) {
+               if (ISINF(x) && x->fp_sign != y->fp_sign)
+                       return (fpu_newnan(fe));
+               return (y);
+       }
+       rd = ((fe->fe_fsr >> FSR_RD_SHIFT) & FSR_RD_MASK);
+       if (ISZERO(y)) {
+               if (rd != FSR_RD_RM)    /* only -0 + -0 gives -0 */
+                       y->fp_sign &= x->fp_sign;
+               else                    /* any -0 operand gives -0 */
+                       y->fp_sign |= x->fp_sign;
+               return (y);
+       }
+       if (ISZERO(x))
+               return (y);
+       /*
+        * We really have two numbers to add, although their signs may
+        * differ.  Make the exponents match, by shifting the smaller
+        * number right (e.g., 1.011 => 0.1011) and increasing its
+        * exponent (2^3 => 2^4).  Note that we do not alter the exponents
+        * of x and y here.
+        */
+       r = &fe->fe_f3;
+       r->fp_class = FPC_NUM;
+       if (x->fp_exp == y->fp_exp) {
+               r->fp_exp = x->fp_exp;
+               r->fp_sticky = 0;
+       } else {
+               if (x->fp_exp < y->fp_exp) {
+                       /*
+                        * Try to avoid subtract case iii (see below).
+                        * This also guarantees that x->fp_sticky = 0.
+                        */
+                       SWAP(x, y);
+               }
+               /* now x->fp_exp > y->fp_exp */
+               r->fp_exp = x->fp_exp;
+               r->fp_sticky = fpu_shr(y, x->fp_exp - y->fp_exp);
+       }
+       r->fp_sign = x->fp_sign;
+       if (x->fp_sign == y->fp_sign) {
+               FPU_DECL_CARRY
+
+               /*
+                * The signs match, so we simply add the numbers.  The result
+                * may be `supernormal' (as big as 1.111...1 + 1.111...1, or
+                * 11.111...0).  If so, a single bit shift-right will fix it
+                * (but remember to adjust the exponent).
+                */
+               /* r->fp_mant = x->fp_mant + y->fp_mant */
+               FPU_ADDS(r->fp_mant[3], x->fp_mant[3], y->fp_mant[3]);
+               FPU_ADDCS(r->fp_mant[2], x->fp_mant[2], y->fp_mant[2]);
+               FPU_ADDCS(r->fp_mant[1], x->fp_mant[1], y->fp_mant[1]);
+               FPU_ADDC(r0, x->fp_mant[0], y->fp_mant[0]);
+               if ((r->fp_mant[0] = r0) >= FP_2) {
+                       (void) fpu_shr(r, 1);
+                       r->fp_exp++;
+               }
+       } else {
+               FPU_DECL_CARRY
+
+               /*
+                * The signs differ, so things are rather more difficult.
+                * H&P would have us negate the negative operand and add;
+                * this is the same as subtracting the negative operand.
+                * This is quite a headache.  Instead, we will subtract
+                * y from x, regardless of whether y itself is the negative
+                * operand.  When this is done one of three conditions will
+                * hold, depending on the magnitudes of x and y:
+                *   case i)   |x| > |y|.  The result is just x - y,
+                *      with x's sign, but it may need to be normalized.
+                *   case ii)  |x| = |y|.  The result is 0 (maybe -0)
+                *      so must be fixed up.
+                *   case iii) |x| < |y|.  We goofed; the result should
+                *      be (y - x), with the same sign as y.
+                * We could compare |x| and |y| here and avoid case iii,
+                * but that would take just as much work as the subtract.
+                * We can tell case iii has occurred by an overflow.
+                *
+                * N.B.: since x->fp_exp >= y->fp_exp, x->fp_sticky = 0.
+                */
+               /* r->fp_mant = x->fp_mant - y->fp_mant */
+               FPU_SET_CARRY(y->fp_sticky);
+               FPU_SUBCS(r3, x->fp_mant[3], y->fp_mant[3]);
+               FPU_SUBCS(r2, x->fp_mant[2], y->fp_mant[2]);
+               FPU_SUBCS(r1, x->fp_mant[1], y->fp_mant[1]);
+               FPU_SUBC(r0, x->fp_mant[0], y->fp_mant[0]);
+               if (r0 < FP_2) {
+                       /* cases i and ii */
+                       if ((r0 | r1 | r2 | r3) == 0) {
+                               /* case ii */
+                               r->fp_class = FPC_ZERO;
+                               r->fp_sign = rd == FSR_RD_RM;
+                               return (r);
+                       }
+               } else {
+                       /*
+                        * Oops, case iii.  This can only occur when the
+                        * exponents were equal, in which case neither
+                        * x nor y have sticky bits set.  Flip the sign
+                        * (to y's sign) and negate the result to get y - x.
+                        */
+#ifdef DIAGNOSTIC
+                       if (x->fp_exp != y->fp_exp || r->fp_sticky)
+                               panic("fpu_add");
+#endif
+                       r->fp_sign = y->fp_sign;
+                       FPU_SUBS(r3, 0, r3);
+                       FPU_SUBCS(r2, 0, r2);
+                       FPU_SUBCS(r1, 0, r1);
+                       FPU_SUBC(r0, 0, r0);
+               }
+               r->fp_mant[3] = r3;
+               r->fp_mant[2] = r2;
+               r->fp_mant[1] = r1;
+               r->fp_mant[0] = r0;
+               if (r0 < FP_1)
+                       fpu_norm(r);
+       }
+       return (r);
+}

diff --git a/usr/src/sys/sparc/fpu/fpu_arith.h b/usr/src/sys/sparc/fpu/fpu_arith.h
new file mode 100644 (file)
index 0000000..0a8b70a
--- /dev/null
+++ b/usr/src/sys/sparc/fpu/fpu_arith.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 1992 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * %sccs.include.redist.c%
+ *
+ *     @(#)fpu_arith.h 7.1 (Berkeley) %G%
+ *
+ * from: $Header: fpu_arith.h,v 1.2 92/06/17 05:41:28 torek Exp $
+ */
+
+/*
+ * Extended-precision arithmetic.
+ *
+ * We hold the notion of a `carry register', which may or may not be a
+ * machine carry bit or register.  On the SPARC, it is just the machine's
+ * carry bit.
+ *
+ * In the worst case, you can compute the carry from x+y as
+ *     (unsigned)(x + y) < (unsigned)x
+ * and from x+y+c as
+ *     ((unsigned)(x + y + c) <= (unsigned)x && (y|c) != 0)
+ * for example.
+ */
+
+/* set up for extended-precision arithemtic */
+#define        FPU_DECL_CARRY
+
+/*
+ * We have three kinds of add:
+ *     add with carry:                                   r = x + y + c
+ *     add (ignoring current carry) and set carry:     c'r = x + y + 0
+ *     add with carry and set carry:                   c'r = x + y + c
+ * The macros use `C' for `use carry' and `S' for `set carry'.
+ * Note that the state of the carry is undefined after ADDC and SUBC,
+ * so if all you have for these is `add with carry and set carry',
+ * that is OK.
+ *
+ * The same goes for subtract, except that we compute x - y - c.
+ *
+ * Finally, we have a way to get the carry into a `regular' variable,
+ * or set it from a value.  SET_CARRY turns 0 into no-carry, nonzero
+ * into carry; GET_CARRY sets its argument to 0 or 1.
+ */
+#define        FPU_ADDC(r, x, y) \
+       asm volatile("addx %1,%2,%0" : "=r"(r) : "r"(x), "r"(y))
+#define        FPU_ADDS(r, x, y) \
+       asm volatile("addcc %1,%2,%0" : "=r"(r) : "r"(x), "r"(y))
+#define        FPU_ADDCS(r, x, y) \
+       asm volatile("addxcc %1,%2,%0" : "=r"(r) : "r"(x), "r"(y))
+#define        FPU_SUBC(r, x, y) \
+       asm volatile("subx %1,%2,%0" : "=r"(r) : "r"(x), "r"(y))
+#define        FPU_SUBS(r, x, y) \
+       asm volatile("subcc %1,%2,%0" : "=r"(r) : "r"(x), "r"(y))
+#define        FPU_SUBCS(r, x, y) \
+       asm volatile("subxcc %1,%2,%0" : "=r"(r) : "r"(x), "r"(y))
+
+#define        FPU_GET_CARRY(r) asm volatile("addx %%g0,%%g0,%0" : "=r"(r))
+#define        FPU_SET_CARRY(v) asm volatile("addcc %0,-1,%%g0" : : "r"(v))
+
+#define        FPU_SHL1_BY_ADD /* shift left 1 faster by ADDC than (a<<1)|(b>>31) */