Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / diag / diaglists / core_qual_pm.diaglist

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: core_qual_pm.diaglist
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<sys(core_qual_pm) name=sys(core_qual_pm)>
<sys(pm_all)>

//Core0_2bank
<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff>

//FAILS OOB
//<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -midas_args=-DPORTABLE_CORE  -midas_args=-DPART_0_BASE=0x200000000   -vcs_run_args=+8_FBDIMMS >
//e2_st_atomic_8t8b_core0_2bank n2_st_atomic_8t8b.s
//</runargs>

<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS>
mpgen_dynamic_caches_core0_2bank           mpgen_dynamic_caches.s
mpgen_dynamic_pwr_mgmt_core0_2bank         mpgen_dynamic_pwr_mgmt.s
mpgen_tso_all_banks_core0_2bank            mpgen_tso_all_banks.s
mpgen_tso_ba_one_bank_core0_2bank          mpgen_tso_ba_one_bank.s
mpgen_tso_ba_all_banks_core0_2bank         mpgen_tso_ba_all_banks.s
mpgen_tso_atomic_all_banks_core0_2bank     mpgen_tso_atomic_all_banks.s
</runargs>

<runargs -vcs_run_args=+8_FBDIMMS>
tlu_fcrand05_ind_14_core0_2bank   tlu_fcrand05_ind_14.s
//FAILS OOB
//fcrand05_rand_88_core0_2bank   fcrand05_rand_88.s -midas_args=-DMULTIPASS=1
//FAILS OOB
//fcrand05_rand_4_core0_2bank    fcrand05_rand_4.s -midas_args=-DMULTIPASS=1
</runargs>

</runargs>

//Core0_4bank
<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff>

<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -midas_args=-DPORTABLE_CORE  -midas_args=-DPART_0_BASE=0x200000000   -vcs_run_args=+8_FBDIMMS >
n2_st_atomic_8t8b_core0_4bank n2_st_atomic_8t8b.s
</runargs>

<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS>
mpgen_dynamic_caches_core0_4bank           mpgen_dynamic_caches.s
mpgen_dynamic_pwr_mgmt_core0_4bank         mpgen_dynamic_pwr_mgmt.s
mpgen_tso_all_banks_core0_4bank            mpgen_tso_all_banks.s
mpgen_tso_ba_one_bank_core0_4bank          mpgen_tso_ba_one_bank.s
mpgen_tso_ba_all_banks_core0_4bank         mpgen_tso_ba_all_banks.s
mpgen_tso_atomic_all_banks_core0_4bank     mpgen_tso_atomic_all_banks.s
</runargs>

<runargs -vcs_run_args=+8_FBDIMMS>
//FAILS TIMEOUT
//tlu_fcrand05_ind_14_core0_4bank   tlu_fcrand05_ind_14.s
//FAILS OOB
//fcrand05_rand_88_core0_4bank   fcrand05_rand_88.s -midas_args=-DMULTIPASS=1
//FAILS ESR
//fcrand05_rand_4_core0_4bank    fcrand05_rand_4.s -midas_args=-DMULTIPASS=1
</runargs>

</runargs>

//Core1_2bank
<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00>

//FAILS OOB
//<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -midas_args=-DPORTABLE_CORE  -midas_args=-DPART_0_BASE=0x200000000   -vcs_run_args=+8_FBDIMMS >
//n2_st_atomic_8t8b_core1_2bank n2_st_atomic_8t8b.s
//</runargs>

<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS>
mpgen_dynamic_caches_core1_2bank           mpgen_dynamic_caches.s
mpgen_dynamic_pwr_mgmt_core1_2bank         mpgen_dynamic_pwr_mgmt.s
mpgen_tso_all_banks_core1_2bank            mpgen_tso_all_banks.s
mpgen_tso_ba_one_bank_core1_2bank          mpgen_tso_ba_one_bank.s
mpgen_tso_ba_all_banks_core1_2bank         mpgen_tso_ba_all_banks.s
mpgen_tso_atomic_all_banks_core1_2bank     mpgen_tso_atomic_all_banks.s
</runargs>

<runargs -vcs_run_args=+8_FBDIMMS>
tlu_fcrand05_ind_14_core1_2bank   tlu_fcrand05_ind_14.s
//FAILS OOB
//fcrand05_rand_88_core1_2bank   fcrand05_rand_88.s -midas_args=-DMULTIPASS=1
//FAILS ESR
//fcrand05_rand_4_core1_2bank    fcrand05_rand_4.s -midas_args=-DMULTIPASS=1
</runargs>

</runargs>

//Core1_4bank
<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x00000000000000ff -finish_mask=00000000000000ff>

<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DPART_0_BASE=0x200000000   -vcs_run_args=+8_FBDIMMS >
n2_st_atomic_8t8b_core1_4bank n2_st_atomic_64t.s
</runargs>

<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS>
mpgen_dynamic_caches_core1_4bank           mpgen_dynamic_caches.s
mpgen_dynamic_pwr_mgmt_core1_4bank         mpgen_dynamic_pwr_mgmt.s
mpgen_tso_all_banks_core1_4bank            mpgen_tso_all_banks.s
mpgen_tso_ba_one_bank_core1_4bank          mpgen_tso_ba_one_bank.s
mpgen_tso_ba_all_banks_core1_4bank         mpgen_tso_ba_all_banks.s
mpgen_tso_atomic_all_banks_core1_4bank     mpgen_tso_atomic_all_banks.s
</runargs>

<runargs -vcs_run_args=+8_FBDIMMS>
tlu_fcrand05_ind_14_core1_4bank   tlu_fcrand05_ind_14.s
//FAILS OOB
//fcrand05_rand_88_core1_4bank   fcrand05_rand_88.s -midas_args=-DMULTIPASS=1
//FAILS ESR
//fcrand05_rand_4_core1_4bank    fcrand05_rand_4.s -midas_args=-DMULTIPASS=1
</runargs>

</runargs>

//Core1_8bank
<runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0x000000000000ff00 -finish_mask=000000000000ff00 >

<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DPART_0_BASE=0x200000000   -vcs_run_args=+8_FBDIMMS >
n2_st_atomic_8t8b_core1_8bank n2_st_atomic_64t.s
</runargs>

<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS>
mpgen_dynamic_caches_core1_8bank           mpgen_dynamic_caches.s
mpgen_dynamic_pwr_mgmt_core1_8bank         mpgen_dynamic_pwr_mgmt.s
mpgen_tso_all_banks_core1_8bank            mpgen_tso_all_banks.s
mpgen_tso_ba_one_bank_core1_8bank          mpgen_tso_ba_one_bank.s
mpgen_tso_ba_all_banks_core1_8bank         mpgen_tso_ba_all_banks.s
mpgen_tso_atomic_all_banks_core1_8bank     mpgen_tso_atomic_all_banks.s
</runargs>

<runargs -vcs_run_args=+8_FBDIMMS -vcs_run_args=+gchkr_off >
tlu_fcrand05_ind_14_core1_8bank   tlu_fcrand05_ind_14.s
//FAILS OOB
//fcrand05_rand_88_core1_8bank   fcrand05_rand_88.s -midas_args=-DMULTIPASS=1
//FAILS ESR
//fcrand05_rand_4_core1_8bank    fcrand05_rand_4.s -midas_args=-DMULTIPASS=1
</runargs>

</runargs>

//Core1257_4bank
<runargs -vcs_run_args=+core_set_mask=a6 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff00ff0000ffff00 -finish_mask=ff00ff0000ffff00>

<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DPART_0_BASE=0x200000000   -vcs_run_args=+8_FBDIMMS >
n2_st_atomic_8t8b_core1257_4bank n2_st_atomic_64t.s
</runargs>

<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS>
//UNFINISHED
//mpgen_dynamic_caches_core1257_4bank           mpgen_dynamic_caches.s
//mpgen_dynamic_pwr_mgmt_core1257_4bank         mpgen_dynamic_pwr_mgmt.s
mpgen_tso_all_banks_core1257_4bank            mpgen_tso_all_banks.s
//mpgen_tso_ba_one_bank_core1257_4bank          mpgen_tso_ba_one_bank.s
mpgen_tso_ba_all_banks_core1257_4bank         mpgen_tso_ba_all_banks.s
mpgen_tso_atomic_all_banks_core1257_4bank     mpgen_tso_atomic_all_banks.s
</runargs>

<runargs -vcs_run_args=+8_FBDIMMS>
tlu_fcrand05_ind_14_core1257_4bank   tlu_fcrand05_ind_14.s
//FAILS OOB
//fcrand05_rand_88_core1257_4bank   fcrand05_rand_88.s -midas_args=-DMULTIPASS=1
//FAILS ESR
//fcrand05_rand_4_core1257_4bank    fcrand05_rand_4.s -midas_args=-DMULTIPASS=1
</runargs>

</runargs>

</sys(pm_all)>
</sys(core_qual_pm)>