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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / fc / FcNiuQual.diaglist
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: FcNiuQual.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<Fc_Niu_Qual name=Fc_Niu_Qual>
36
37// ****************************************************************************
38// NIU PIO Read & Write
39// ****************************************************************************
40//<FcNiuPio_Qual name=FcNiuPio_Qual>
41
42FcNiuPioWrRd basic_niu_pio_mask.s -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1
43
44//</FcNiuPio_Qual>
45// ****************************************************************************
46
47
48// ****************************************************************************
49// 10G -> MAC0 -> NIU Tx.
50// ****************************************************************************
51//<FcNiu10GMac0Tx_Qual name=FcNiu10GMac0Tx_Qual>
52
53<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -vcs_run_args=+MAC_SPEED0=10000 >
54<runargs -vcs_run_args=+MAC_SPEED1=10000 >
55<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
56<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
57<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST >
58<runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
59<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
60
61FcNiu10GMac0Tx FcNiuBasicTx.s
62
63<runargs -midas_args=-DNIU_TX_DMA_NUM=15 -midas_args=-DNIU_TX_DMA_ACT_LIST=0x8000 >
64<runargs -midas_args=-DNIU_TX_PKT_CNT=0x19 -midas_args=-Dloop_count=20 -midas_args=-DJUMBO_FRAME_EN >
65<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_PKT_LEN=200 -midas_args=-Dloop_count=100 -midas_args=-DJUMBO_FRAME_EN >
66
67FcNiuTx_DMA15_PktCnt25_PktLen_Gather FcNiuBasicTx.s
68
69<runargs -midas_args=-DXLATE_ON -vcs_run_args=+USE_RANDOM_ADDRESS >
70FcNiuTx_DMA15_PktCnt25_PktLen_Gather_Xlate FcNiuBasicTx.s
71</runargs>
72
73</runargs>
74</runargs>
75</runargs>
76
77
78</runargs>
79</runargs>
80</runargs>
81</runargs>
82</runargs>
83</runargs>
84</runargs>
85
86//</FcNiu10GMac0Tx_Qual>
87// ****************************************************************************
88
89// ****************************************************************************
90// 10G -> MAC0 -> NIU Rx.
91// ****************************************************************************
92//<FcNiu10GMac0Rx_Qual name=FcNiu10GMac0Rx_Qual>
93
94<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
95<runargs -vcs_run_args=+MAC_SPEED1=10000 >
96<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
97<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
98<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+RX_TEST -midas_args=-DRX_TEST >
99<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
100<runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=10 >
101<runargs -vcs_run_args=+no_verilog_finish >
102<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
103
104FcNiu10GMac0Rx FcNiuBasicRx_sweep1.s
105
106<runargs -midas_args=-DRXDMA_CHNL=0x1 >
107FcNiuRx_DMA1 FcNiuBasicRx_sweep1.s
108
109<runargs -midas_args=-DXLATE_ON >
110FcNiuRx_DMA1_Xlate FcNiuBasicRx_sweep1.s
111
112</runargs>
113</runargs>
114
115
116</runargs>
117</runargs>
118</runargs>
119</runargs>
120</runargs>
121</runargs>
122</runargs>
123</runargs>
124</runargs>
125
126//</FcNiu10GMac0Rx_Qual>
127// ****************************************************************************
128
129// ****************************************************************************
130// 10G -> MAC1 -> NIU Tx.
131// ****************************************************************************
132//<FcNiu10GMac1Tx_Qual name=FcNiu10GMac1Tx_Qual>
133
134<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
135<runargs -vcs_run_args=+MAC_SPEED1=10000 >
136<runargs -vcs_run_args=+GET_MAC_PORTS=1 >
137<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
138<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+TX_TEST >
139<runargs -midas_args=-DTX_TEST -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
140<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
141<runargs -midas_args=-DMAC_ID=1 >
142
143FcNiu10GMac1Tx FcNiuBasicTx.s
144
145<runargs -midas_args=-DNIU_TX_DMA_NUM=15 -midas_args=-DNIU_TX_DMA_ACT_LIST=0x8000 >
146<runargs -midas_args=-DNIU_TX_PKT_CNT=0x19 >
147<runargs -vcs_run_args=+TX_GATHER -vcs_run_args=+TX_PKT_LEN=200 -midas_args=-Dloop_count=100 -midas_args=-DJUMBO_FRAME_EN >
148
149FcNiuTx_McPort1_DMA15_PktCnt25_PktLen_Gather FcNiuBasicTx.s
150
151</runargs>
152</runargs>
153</runargs>
154
155</runargs>
156</runargs>
157</runargs>
158</runargs>
159</runargs>
160</runargs>
161</runargs>
162</runargs>
163
164//</FcNiu10GMac1Tx_Qual>
165// ****************************************************************************
166
167// ****************************************************************************
168// 10G -> MAC1 -> NIU Rx.
169// ****************************************************************************
170//<FcNiu10GMac1Rx_Qual name=FcNiu10GMac1Rx_Qual>
171
172<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=1 >
173<runargs -vcs_run_args=+MAC_SPEED1=10000 >
174<runargs -vcs_run_args=+GET_MAC_PORTS=1 >
175<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
176<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+RX_TEST -midas_args=-DRX_TEST >
177<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
178<runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=10 >
179<runargs -midas_args=-DMAC_ID=1 >
180<runargs -vcs_run_args=+no_verilog_finish >
181<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
182
183FcNiu10GMac1Rx FcNiuBasicRx_sweep1.s
184
185</runargs>
186</runargs>
187</runargs>
188</runargs>
189</runargs>
190</runargs>
191</runargs>
192</runargs>
193</runargs>
194</runargs>
195
196//</FcNiu10GMac1Rx_Qual>
197// ****************************************************************************
198
199// ****************************************************************************
200// NIU Tx + Rx (Multi-threaded).
201// ****************************************************************************
202//<FcNiuTxRx_Qual name=FcNiuTxRx_Qual>
203
204<runargs -sas -midas_args=-DCMP_THREAD_START=0x1 -vcs_run_args=+MAC_SPEED0=10000 -finish_mask=3 >
205<runargs -vcs_run_args=+MAC_SPEED1=10000 >
206<runargs -vcs_run_args=+GET_MAC_PORTS=0 >
207<runargs -vcs_run_args=+PCS_SERDES -vcs_run_args=+displaySysRdWr >
208<runargs -vcs_run_args=+ORIG_META -vcs_run_args=+RX_TEST -midas_args=-DRX_TEST >
209<runargs -midas_args=-DMAC_SPEED0=10000 -midas_args=-DMAC_SPEED1=10000 -midas_args=-DPCS_SERDES >
210<runargs -vcs_run_args=+TX_TEST -midas_args=-DTX_TEST >
211<runargs -midas_args=-DRXMAC_PKTCNT=0xa -vcs_run_args=+RXMAC_PKTCNT=10 >
212<runargs -midas_args=-DMAC_ID=0 >
213<runargs -vcs_run_args=+no_verilog_finish >
214<runargs -vcs_run_args=+PEU_TEST -vcs_run_args=+ENABLE_PCIE_LINK_TRAINING -midas_args=-DENABLE_PCIE_LINK_TRAINING >
215
216FcNiuBasicTxRx FcNiuBasicTxRx.s
217
218</runargs>
219</runargs>
220</runargs>
221</runargs>
222</runargs>
223</runargs>
224</runargs>
225</runargs>
226</runargs>
227</runargs>
228</runargs>
229
230//</FcNiuTxRx_Qual>
231// ****************************************************************************
232
233</Fc_Niu_Qual>
Full OpenSPARC design & verification tarball including full HDL.