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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / pm / pm_mcu.diaglist
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: pm_mcu.diaglist
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35<sys(mcu_pm) name=sys(mcu_pm)>
36<sys(pm_all)>
37
38<sys(pm_mcu)>
39
40<runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+8_FBDIMMS -midas_args=-DSYNC_THREADS -vcs_run_args=+mon+mcu_fmon=1=1 -vcs_run_args=+debug -vcs_run_args=+gchkr_off>
41
42
43//Core0_2bank
44<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -vcs_run_args=+STACK_DIMM>
45n2_pm_mcu_cmda_Core0_2Bank n2_pm_mcu_cmda_2bank.s
46</runargs>
47
48<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff >
49<runargs -midas_args=-DL2_DIRECT_MAP>
50
51n2_pm_mcu_all_th_wr_Core0_2bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0
52n2_pm_mcu_all_th_rd_Core0_2bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0
53n2_pm_mcu_all_th_wrrd_Core0_2bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0
54n2_pm_mcu_diff_th_wr_rd_Core0_2bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0
55
56n2_pm_mcu_all_th_wr_Core0_2bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1
57n2_pm_mcu_all_th_rd_Core0_2bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1
58n2_pm_mcu_all_th_wrrd_Core0_2bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1
59n2_pm_mcu_diff_th_wr_rd_Core0_2bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1
60
61n2_pm_all_dimm_Core0_2bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_2BANK -midas_args=-DBANK0
62n2_pm_all_dimm_Core0_2bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_2BANK -midas_args=-DBANK1
63
64n2_pm_all_dimm_rdwr_Core0_2bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK -midas_args=-DBANK0
65n2_pm_all_dimm_rdwr_Core0_2bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK -midas_args=-DBANK1
66
67n2_pm_all_dimm_rdwr_2_Core0_2bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK -midas_args=-DBANK0
68n2_pm_all_dimm_rdwr_2_Core0_2bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK -midas_args=-DBANK1
69
70n2_pm_all_dimm_rdwr_3_Core0_2bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK
71n2_pm_all_dimm_rdwr_4_Core0_2bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK
72
73n2_pm_all_dimm_rdwr_5_Core0_2bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK
74n2_pm_all_dimm_rdwr_6_Core0_2bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK
75
76// fails DBU; n2_mcu_0_all_bcopy_all_banks_Core0_2bank n2_mcu_0_all_bcopy_all_banks.s
77</runargs>
78
79n2_pm_all_dimm_rdwr_3_Core0_2bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK
80n2_pm_all_dimm_rdwr_4_Core0_2bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK
81
82n2_pm_all_dimm_rdwr_5_Core0_2bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK
83n2_pm_all_dimm_rdwr_6_Core0_2bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK
84</runargs>
85
86
87//Core0_4bank
88<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -vcs_run_args=+STACK_DIMM>
89n2_pm_mcu_cmda_Core0_4Bank n2_pm_mcu_cmda_4bank.s
90</runargs>
91
92<runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff >
93<runargs -midas_args=-DL2_DIRECT_MAP>
94n2_pm_mcu_all_th_wr_Core0_4bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0
95n2_pm_mcu_all_th_rd_Core0_4bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0
96n2_pm_mcu_all_th_wrrd_Core0_4bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0
97n2_pm_mcu_diff_th_wr_rd_Core0_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0
98
99n2_pm_mcu_all_th_wr_Core0_4bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1
100n2_pm_mcu_all_th_rd_Core0_4bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1
101n2_pm_mcu_all_th_wrrd_Core0_4bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1
102n2_pm_mcu_diff_th_wr_rd_Core0_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1
103
104n2_pm_all_dimm_Core0_4bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
105n2_pm_all_dimm_Core0_4bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
106
107n2_pm_all_dimm_rdwr_Core0_4bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
108n2_pm_all_dimm_rdwr_Core0_4bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
109
110n2_pm_all_dimm_rdwr_2_Core0_4bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
111n2_pm_all_dimm_rdwr_2_Core0_4bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
112
113n2_pm_all_dimm_rdwr_5_Core0_4bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
114n2_pm_all_dimm_rdwr_6_Core0_4bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
115
116n2_mcu_0_all_bcopy_all_banks_Core0_4bank n2_mcu_0_all_bcopy_all_banks.s
117</runargs>
118
119n2_pm_all_dimm_rdwr_3_Core0_4bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
120n2_pm_all_dimm_rdwr_4_Core0_4bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK
121
122n2_pm_all_dimm_rdwr_5_Core0_4bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
123n2_pm_all_dimm_rdwr_6_Core0_4bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
124</runargs>
125
126//Core1_2bank
127<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+STACK_DIMM>
128n2_pm_mcu_cmda_Core1_2Bank n2_pm_mcu_cmda_2bank.s
129</runargs>
130
131<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 >
132<runargs -midas_args=-DL2_DIRECT_MAP>
133n2_pm_mcu_all_th_wr_Core1_2bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0
134n2_pm_mcu_all_th_rd_Core1_2bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0
135n2_pm_mcu_all_th_wrrd_Core1_2bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0
136n2_pm_mcu_diff_th_wr_rd_Core1_2bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0
137
138n2_pm_mcu_all_th_wr_Core1_2bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1
139n2_pm_mcu_all_th_rd_Core1_2bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1
140n2_pm_mcu_all_th_wrrd_Core1_2bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1
141n2_pm_mcu_diff_th_wr_rd_Core1_2bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1
142
143n2_pm_all_dimm_Core1_2bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_2BANK -midas_args=-DBANK0
144n2_pm_all_dimm_Core1_2bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_2BANK -midas_args=-DBANK1
145
146n2_pm_all_dimm_rdwr_Core1_2bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK -midas_args=-DBANK0
147n2_pm_all_dimm_rdwr_Core1_2bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK -midas_args=-DBANK1
148
149n2_pm_all_dimm_rdwr_2_Core1_2bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK -midas_args=-DBANK0
150n2_pm_all_dimm_rdwr_2_Core1_2bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK -midas_args=-DBANK1
151
152n2_pm_all_dimm_rdwr_3_Core1_2bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK
153n2_pm_all_dimm_rdwr_4_Core1_2bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK
154
155n2_pm_all_dimm_rdwr_5_Core1_2bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK
156n2_pm_all_dimm_rdwr_6_Core1_2bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK
157
158// fails DBU; n2_mcu_0_all_bcopy_all_banks_Core1_2bank n2_mcu_0_all_bcopy_all_banks.s
159</runargs>
160
161n2_pm_all_dimm_rdwr_3_Core1_2bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK
162n2_pm_all_dimm_rdwr_4_Core1_2bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK
163
164n2_pm_all_dimm_rdwr_5_Core1_2bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK
165n2_pm_all_dimm_rdwr_6_Core1_2bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK
166</runargs>
167
168//Core1_4bank
169<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+STACK_DIMM>
170n2_pm_mcu_cmda_Core1_4Bank n2_pm_mcu_cmda_4bank.s
171</runargs>
172
173<runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 >
174<runargs -midas_args=-DL2_DIRECT_MAP>
175n2_pm_mcu_all_th_wr_Core1_4bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0
176n2_pm_mcu_all_th_rd_Core1_4bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0
177n2_pm_mcu_all_th_wrrd_Core1_4bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0
178n2_pm_mcu_diff_th_wr_rd_Core1_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0
179
180n2_pm_mcu_all_th_wr_Core1_4bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1
181n2_pm_mcu_all_th_rd_Core1_4bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1
182n2_pm_mcu_all_th_wrrd_Core1_4bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1
183n2_pm_mcu_diff_th_wr_rd_Core1_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1
184
185n2_pm_all_dimm_Core1_4bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
186n2_pm_all_dimm_Core1_4bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
187
188n2_pm_all_dimm_rdwr_Core1_4bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
189n2_pm_all_dimm_rdwr_Core1_4bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
190
191n2_pm_all_dimm_rdwr_2_Core1_4bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
192n2_pm_all_dimm_rdwr_2_Core1_4bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
193
194n2_pm_all_dimm_rdwr_3_Core1_4bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
195n2_pm_all_dimm_rdwr_4_Core1_4bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK
196
197n2_pm_all_dimm_rdwr_5_Core1_4bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
198n2_pm_all_dimm_rdwr_6_Core1_4bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
199
200n2_mcu_0_all_bcopy_all_banks_Core1_4bank n2_mcu_0_all_bcopy_all_banks.s
201</runargs>
202
203n2_pm_all_dimm_rdwr_3_Core1_4bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
204n2_pm_all_dimm_rdwr_4_Core1_4bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK
205
206n2_pm_all_dimm_rdwr_5_Core1_4bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
207n2_pm_all_dimm_rdwr_6_Core1_4bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
208</runargs>
209
210//Core1_8bank
211<runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+STACK_DIMM>
212n2_pm_mcu_cmda_Core1_8Bank n2_pm_mcu_cmda_8bank.s
213</runargs>
214
215<runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 -midas_args=-DL2_DIRECT_MAP>
216<runargs -midas_args=-DL2_DIRECT_MAP>
217n2_pm_mcu_all_th_wr_Core1_8bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0
218n2_pm_mcu_all_th_rd_Core1_8bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0
219n2_pm_mcu_all_th_wrrd_Core1_8bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0
220n2_pm_mcu_diff_th_wr_rd_Core1_8bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0
221
222
223n2_pm_mcu_all_th_wr_Core1_8bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1
224n2_pm_mcu_all_th_rd_Core1_8bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1
225n2_pm_mcu_all_th_wrrd_Core1_8bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1
226n2_pm_mcu_diff_th_wr_rd_Core1_8bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1
227
228n2_pm_all_dimm_Core1_8bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_8BANK -midas_args=-DBANK0
229n2_pm_all_dimm_Core1_8bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_8BANK -midas_args=-DBANK1
230
231n2_pm_all_dimm_rdwr_Core1_8bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_8BANK -midas_args=-DBANK0
232n2_pm_all_dimm_rdwr_Core1_8bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_8BANK -midas_args=-DBANK1
233
234n2_pm_all_dimm_rdwr_2_Core1_8bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_8BANK -midas_args=-DBANK0
235n2_pm_all_dimm_rdwr_2_Core1_8bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_8BANK -midas_args=-DBANK1
236
237n2_pm_all_dimm_rdwr_3_Core1_8bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_8BANK
238n2_pm_all_dimm_rdwr_4_Core1_8bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_8BANK
239
240n2_pm_all_dimm_rdwr_5_Core1_8bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_8BANK
241n2_pm_all_dimm_rdwr_6_Core1_8bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_8BANK
242
243
244n2_mcu_0_all_bcopy_all_banks_Core1_8bank n2_mcu_0_all_bcopy_all_banks.s
245</runargs>
246
247n2_pm_all_dimm_rdwr_3_Core1_8bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_8BANK
248n2_pm_all_dimm_rdwr_4_Core1_8bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_8BANK
249
250n2_pm_all_dimm_rdwr_5_Core1_8bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_8BANK
251n2_pm_all_dimm_rdwr_6_Core1_8bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_8BANK
252</runargs>
253
254//Core1257_4bank
255<runargs -vcs_run_args=+core_set_mask=a6 -midas_args=-DCMP_THREAD_START=0x0100010000010100 -finish_mask=0100010000010100 -vcs_run_args=+STACK_DIMM>
256n2_pm_mcu_cmda_Core1257_4Bank n2_pm_mcu_cmda_4bank.s
257</runargs>
258
259<runargs -vcs_run_args=+core_set_mask=a6 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff00ff0000ffff00 -finish_mask=ff00ff0000ffff00 >
260<runargs -midas_args=-DL2_DIRECT_MAP>
261n2_pm_mcu_all_th_wr_Core1257_4bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0
262n2_pm_mcu_all_th_rd_Core1257_4bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0
263n2_pm_mcu_all_th_wrrd_Core1257_4bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0
264n2_pm_mcu_diff_th_wr_rd_Core1257_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0
265
266n2_pm_mcu_all_th_wr_Core1257_4bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1
267n2_pm_mcu_all_th_rd_Core1257_4bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1
268n2_pm_mcu_all_th_wrrd_Core1257_4bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1
269n2_pm_mcu_diff_th_wr_rd_Core1257_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1
270
271n2_pm_all_dimm_Core1257_4bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
272n2_pm_all_dimm_Core1257_4bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
273
274n2_pm_all_dimm_rdwr_Core1257_4bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
275n2_pm_all_dimm_rdwr_Core1257_4bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
276
277n2_pm_all_dimm_rdwr_2_Core1257_4bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK0
278n2_pm_all_dimm_rdwr_2_Core1257_4bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK1
279
280n2_pm_all_dimm_rdwr_3_Core1257_4bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
281n2_pm_all_dimm_rdwr_4_Core1257_4bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK
282
283n2_pm_all_dimm_rdwr_5_Core1257_4bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
284n2_pm_all_dimm_rdwr_6_Core1257_4bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
285
286// long running n2_mcu_0_all_bcopy_all_banks_Core1257_4bank n2_mcu_0_all_bcopy_all_banks.s
287</runargs>
288
289n2_pm_all_dimm_rdwr_3_Core1257_4bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK
290n2_pm_all_dimm_rdwr_4_Core1257_4bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK
291
292n2_pm_all_dimm_rdwr_5_Core1257_4bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK
293n2_pm_all_dimm_rdwr_6_Core1257_4bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK
294</runargs>
295
296
297
298</runargs>
299
300</sys(pm_mcu)>
301
302
303</sys(pm_all)>
304</sys(mcu_pm)>
305
Full OpenSPARC design & verification tarball including full HDL.