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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / coverage / l2sat / l2_buffer_hits_sample.vrhpal
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2_buffer_hits_sample.vrhpal
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
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13// This program is distributed in the hope that it will be useful,
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16// GNU General Public License for more details.
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34// ========== Copyright Header End ============================================
35wildcard state LOAD_mb ( {4'b1000, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
36wildcard state LOAD_fb ( {4'b0100, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
37wildcard state LOAD_wb ( {4'b0010, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
38wildcard state LOAD_rb ( {4'b0001, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
39wildcard state LOAD_mb_fb ( {4'b1100, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
40wildcard state LOAD_mb_wb ( {4'b1010, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
41wildcard state LOAD_mb_rb ( {4'b1001, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
42wildcard bad_state LOAD_fb_wb ( {4'b0110, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
43wildcard bad_state LOAD_fb_rb ( {4'b0101, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
44wildcard bad_state LOAD_wb_rb ( {4'b0011, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
45wildcard bad_state LOAD_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
46wildcard bad_state LOAD_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
47wildcard bad_state LOAD_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
48wildcard bad_state LOAD_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
49wildcard bad_state LOAD_mb_fb_wb_rb ( {4'b1111, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
50
51// PREFETCH vld diag reqtype nc jbi cputh inv pf bis
52wildcard state PREFETCH_mb ( {4'b1000, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
53wildcard state PREFETCH_fb ( {4'b0100, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
54wildcard state PREFETCH_wb ( {4'b0010, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
55wildcard state PREFETCH_rb ( {4'b0001, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
56wildcard state PREFETCH_mb_fb ( {4'b1100, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
57wildcard state PREFETCH_mb_wb ( {4'b1010, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
58wildcard state PREFETCH_mb_rb ( {4'b1001, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
59wildcard bad_state PREFETCH_fb_wb ( {4'b0110, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
60wildcard bad_state PREFETCH_fb_rb ( {4'b0101, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
61wildcard bad_state PREFETCH_wb_rb ( {4'b0011, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
62wildcard bad_state PREFETCH_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
63wildcard bad_state PREFETCH_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
64wildcard bad_state PREFETCH_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
65wildcard bad_state PREFETCH_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
66wildcard bad_state PREFETCH_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} );
67
68// IMISS vld diag reqtype nc jbi cputh inv pf bis
69wildcard state IMISS_mb ( {4'b1000, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
70wildcard state IMISS_fb ( {4'b0100, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
71wildcard state IMISS_wb ( {4'b0010, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
72wildcard state IMISS_rb ( {4'b0001, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
73wildcard state IMISS_mb_fb ( {4'b1100, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
74wildcard state IMISS_mb_wb ( {4'b1010, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
75wildcard state IMISS_mb_rb ( {4'b1001, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
76wildcard bad_state IMISS_fb_wb ( {4'b0110, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
77wildcard bad_state IMISS_fb_rb ( {4'b0101, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
78wildcard bad_state IMISS_wb_rb ( {4'b0011, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
79wildcard bad_state IMISS_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
80wildcard bad_state IMISS_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
81wildcard bad_state IMISS_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
82wildcard bad_state IMISS_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
83wildcard bad_state IMISS_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
84
85// STORE vld diag reqtype nc jbi cputh inv pf bis
86wildcard state STORE_mb ( {4'b1000, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
87wildcard state STORE_fb ( {4'b0100, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
88wildcard state STORE_wb ( {4'b0010, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
89wildcard state STORE_rb ( {4'b0001, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
90wildcard state STORE_mb_fb ( {4'b1100, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
91wildcard state STORE_mb_wb ( {4'b1010, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
92wildcard state STORE_mb_rb ( {4'b1001, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
93wildcard bad_state STORE_fb_wb ( {4'b0110, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
94wildcard bad_state STORE_fb_rb ( {4'b0101, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
95wildcard bad_state STORE_wb_rb ( {4'b0011, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
96wildcard bad_state STORE_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
97wildcard bad_state STORE_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
98wildcard bad_state STORE_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
99wildcard bad_state STORE_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
100wildcard bad_state STORE_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
101
102// BLKSTORE vld diag reqtype nc jbi cputh inv pf bis
103wildcard state BLKSTORE_mb ( {4'b1000, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
104wildcard state BLKSTORE_fb ( {4'b0100, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
105wildcard state BLKSTORE_wb ( {4'b0010, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
106wildcard state BLKSTORE_rb ( {4'b0001, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
107wildcard state BLKSTORE_mb_fb ( {4'b1100, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
108wildcard state BLKSTORE_mb_wb ( {4'b1010, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
109wildcard state BLKSTORE_mb_rb ( {4'b1001, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
110wildcard bad_state BLKSTORE_fb_wb ( {4'b0110, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
111wildcard bad_state BLKSTORE_fb_rb ( {4'b0101, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
112wildcard bad_state BLKSTORE_wb_rb ( {4'b0011, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
113wildcard bad_state BLKSTORE_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
114wildcard bad_state BLKSTORE_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
115wildcard bad_state BLKSTORE_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
116wildcard bad_state BLKSTORE_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
117wildcard bad_state BLKSTORE_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} );
118
119// BLKINITST vld diag reqtype nc jbi cputh inv pf bis
120wildcard state BLKINITST_mb ( {4'b1000, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
121wildcard state BLKINITST_fb ( {4'b0100, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
122wildcard state BLKINITST_wb ( {4'b0010, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
123wildcard state BLKINITST_rb ( {4'b0001, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
124wildcard state BLKINITST_mb_fb ( {4'b1100, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
125wildcard state BLKINITST_mb_wb ( {4'b1010, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
126wildcard state BLKINITST_mb_rb ( {4'b1001, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
127wildcard bad_state BLKINITST_fb_wb ( {4'b0110, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
128wildcard bad_state BLKINITST_fb_rb ( {4'b0101, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
129wildcard bad_state BLKINITST_wb_rb ( {4'b0011, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
130wildcard bad_state BLKINITST_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
131wildcard bad_state BLKINITST_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
132wildcard bad_state BLKINITST_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
133wildcard bad_state BLKINITST_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
134wildcard bad_state BLKINITST_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} );
135
136// CAS1 vld diag reqtype nc jbi cputh inv pf bis
137wildcard state CAS1_mb ( {4'b1000, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
138wildcard state CAS1_fb ( {4'b0100, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
139wildcard state CAS1_wb ( {4'b0010, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
140wildcard state CAS1_rb ( {4'b0001, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
141wildcard state CAS1_mb_fb ( {4'b1100, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
142wildcard state CAS1_mb_wb ( {4'b1010, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
143wildcard state CAS1_mb_rb ( {4'b1001, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
144wildcard bad_state CAS1_fb_wb ( {4'b0110, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
145wildcard bad_state CAS1_fb_rb ( {4'b0101, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
146wildcard bad_state CAS1_wb_rb ( {4'b0011, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
147wildcard bad_state CAS1_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
148wildcard bad_state CAS1_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
149wildcard bad_state CAS1_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
150wildcard bad_state CAS1_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
151wildcard bad_state CAS1_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
152
153// CAS2 vld diag reqtype nc jbi cputh inv pf bis
154wildcard state CAS2_mb ( {4'b1000, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
155wildcard state CAS2_fb ( {4'b0100, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
156wildcard state CAS2_wb ( {4'b0010, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
157wildcard state CAS2_rb ( {4'b0001, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
158wildcard state CAS2_mb_fb ( {4'b1100, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
159wildcard state CAS2_mb_wb ( {4'b1010, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
160wildcard state CAS2_mb_rb ( {4'b1001, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
161wildcard bad_state CAS2_fb_wb ( {4'b0110, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
162wildcard bad_state CAS2_fb_rb ( {4'b0101, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
163wildcard bad_state CAS2_wb_rb ( {4'b0011, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
164wildcard bad_state CAS2_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
165wildcard bad_state CAS2_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
166wildcard bad_state CAS2_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
167wildcard bad_state CAS2_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
168wildcard bad_state CAS2_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
169
170// SWAP vld diag reqtype nc jbi cputh inv pf bis
171wildcard state SWAP_mb ( {4'b1000, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
172wildcard state SWAP_fb ( {4'b0100, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
173wildcard state SWAP_wb ( {4'b0010, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
174wildcard state SWAP_rb ( {4'b0001, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
175wildcard state SWAP_mb_fb ( {4'b1100, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
176wildcard state SWAP_mb_wb ( {4'b1010, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
177wildcard state SWAP_mb_rb ( {4'b1001, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
178wildcard bad_state SWAP_fb_wb ( {4'b0110, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
179wildcard bad_state SWAP_fb_rb ( {4'b0101, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
180wildcard bad_state SWAP_wb_rb ( {4'b0011, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
181wildcard bad_state SWAP_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
182wildcard bad_state SWAP_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
183wildcard bad_state SWAP_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
184wildcard bad_state SWAP_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
185wildcard bad_state SWAP_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
186
187// STRLOAD vld diag reqtype nc jbi cputh inv pf bis
188wildcard state STRLOAD_mb ( {4'b1000, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
189wildcard state STRLOAD_fb ( {4'b0100, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
190wildcard state STRLOAD_wb ( {4'b0010, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
191wildcard state STRLOAD_rb ( {4'b0001, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
192wildcard state STRLOAD_mb_fb ( {4'b1100, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
193wildcard state STRLOAD_mb_wb ( {4'b1010, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
194wildcard state STRLOAD_mb_rb ( {4'b1001, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
195wildcard bad_state STRLOAD_fb_wb ( {4'b0110, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
196wildcard bad_state STRLOAD_fb_rb ( {4'b0101, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
197wildcard bad_state STRLOAD_wb_rb ( {4'b0011, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
198wildcard bad_state STRLOAD_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
199wildcard bad_state STRLOAD_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
200wildcard bad_state STRLOAD_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
201wildcard bad_state STRLOAD_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
202wildcard bad_state STRLOAD_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
203
204// STRST vld diag reqtype nc jbi cputh inv pf bis
205wildcard state STRST_mb ( {4'b1000, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
206wildcard state STRST_fb ( {4'b0100, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
207wildcard state STRST_wb ( {4'b0010, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
208wildcard state STRST_rb ( {4'b0001, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
209wildcard state STRST_mb_fb ( {4'b1100, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
210wildcard state STRST_mb_wb ( {4'b1010, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
211wildcard state STRST_mb_rb ( {4'b1001, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
212wildcard bad_state STRST_fb_wb ( {4'b0110, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
213wildcard bad_state STRST_fb_rb ( {4'b0101, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
214wildcard bad_state STRST_wb_rb ( {4'b0011, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
215wildcard bad_state STRST_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
216wildcard bad_state STRST_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
217wildcard bad_state STRST_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
218wildcard bad_state STRST_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
219wildcard bad_state STRST_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
220
221/*
222// FWDRQ_LOAD vld diag reqtype nc jbi cputh inv pf bis
223wildcard state FWDRQ_LOAD_mb ( {4'b1000, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
224wildcard state FWDRQ_LOAD_fb ( {4'b0100, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
225wildcard state FWDRQ_LOAD_wb ( {4'b0010, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
226wildcard state FWDRQ_LOAD_rb ( {4'b0001, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
227wildcard state FWDRQ_LOAD_mb_fb ( {4'b1100, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
228wildcard state FWDRQ_LOAD_mb_wb ( {4'b1010, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
229wildcard state FWDRQ_LOAD_mb_rb ( {4'b1001, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
230wildcard bad_state FWDRQ_LOAD_fb_wb ( {4'b0110, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
231wildcard bad_state FWDRQ_LOAD_fb_rb ( {4'b0101, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
232wildcard bad_state FWDRQ_LOAD_wb_rb ( {4'b0011, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
233wildcard bad_state FWDRQ_LOAD_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
234wildcard bad_state FWDRQ_LOAD_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
235wildcard bad_state FWDRQ_LOAD_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
236wildcard bad_state FWDRQ_LOAD_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
237wildcard bad_state FWDRQ_LOAD_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
238
239// FWDRQ_STORE vld diag reqtype nc jbi cputh inv pf bis
240wildcard state FWDRQ_STORE_mb ( {4'b1000, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
241wildcard state FWDRQ_STORE_fb ( {4'b0100, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
242wildcard state FWDRQ_STORE_wb ( {4'b0010, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
243wildcard state FWDRQ_STORE_rb ( {4'b0001, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
244wildcard state FWDRQ_STORE_mb_fb ( {4'b1100, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
245wildcard state FWDRQ_STORE_mb_wb ( {4'b1010, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
246wildcard state FWDRQ_STORE_mb_rb ( {4'b1001, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
247wildcard bad_state FWDRQ_STORE_fb_wb ( {4'b0110, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
248wildcard bad_state FWDRQ_STORE_fb_rb ( {4'b0101, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
249wildcard bad_state FWDRQ_STORE_wb_rb ( {4'b0011, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
250wildcard bad_state FWDRQ_STORE_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
251wildcard bad_state FWDRQ_STORE_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
252wildcard bad_state FWDRQ_STORE_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
253wildcard bad_state FWDRQ_STORE_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
254wildcard bad_state FWDRQ_STORE_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} );
255*/
256
257// RDD vld diag reqtype nc jbi
258wildcard state RDD_mb ( {4'b1000, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
259wildcard state RDD_fb ( {4'b0100, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
260wildcard state RDD_wb ( {4'b0010, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
261wildcard state RDD_rb ( {4'b0001, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
262wildcard state RDD_mb_fb ( {4'b1100, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
263wildcard state RDD_mb_wb ( {4'b1010, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
264wildcard state RDD_mb_rb ( {4'b1001, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
265wildcard bad_state RDD_fb_wb ( {4'b0110, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
266wildcard bad_state RDD_fb_rb ( {4'b0101, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
267wildcard bad_state RDD_wb_rb ( {4'b0011, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
268wildcard bad_state RDD_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
269wildcard bad_state RDD_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
270wildcard bad_state RDD_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
271wildcard bad_state RDD_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
272wildcard bad_state RDD_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} );
273
274// WR8 vld diag reqtype nc jbi
275wildcard state WR8_mb ( {4'b1000, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
276wildcard state WR8_fb ( {4'b0100, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
277wildcard state WR8_wb ( {4'b0010, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
278wildcard state WR8_rb ( {4'b0001, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
279wildcard state WR8_mb_fb ( {4'b1100, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
280wildcard state WR8_mb_wb ( {4'b1010, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
281wildcard state WR8_mb_rb ( {4'b1001, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
282wildcard bad_state WR8_fb_wb ( {4'b0110, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
283wildcard bad_state WR8_fb_rb ( {4'b0101, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
284wildcard bad_state WR8_wb_rb ( {4'b0011, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
285wildcard bad_state WR8_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
286wildcard bad_state WR8_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
287wildcard bad_state WR8_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
288wildcard bad_state WR8_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
289wildcard bad_state WR8_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} );
290
291// WRI vld diag reqtype nc jbi
292wildcard state WRI_mb ( {4'b1000, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
293wildcard state WRI_fb ( {4'b0100, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
294wildcard state WRI_wb ( {4'b0010, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
295wildcard state WRI_rb ( {4'b0001, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
296wildcard state WRI_mb_fb ( {4'b1100, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
297wildcard state WRI_mb_wb ( {4'b1010, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
298wildcard state WRI_mb_rb ( {4'b1001, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
299wildcard bad_state WRI_fb_wb ( {4'b0110, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
300wildcard bad_state WRI_fb_rb ( {4'b0101, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
301wildcard bad_state WRI_wb_rb ( {4'b0011, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
302wildcard bad_state WRI_mb_fb_wb ( {4'b1110, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
303wildcard bad_state WRI_mb_fb_rb ( {4'b1101, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
304wildcard bad_state WRI_mb_wb_rb ( {4'b1011, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
305wildcard bad_state WRI_fb_wb_rb ( {4'b0111, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
306wildcard bad_state WRI_mb_fb_wb_rb( {4'b1111, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} );
Full OpenSPARC design & verification tarball including full HDL.