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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: baseAsmToVeraIntf.vrh | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC__TMP_BASEASMTOVERAINTF_VRH | |
36 | #define INC__TMP_BASEASMTOVERAINTF_VRH | |
37 | ||
38 | ||
39 | extern virtual class BaseAsmToVeraIntf { | |
40 | task generic_ev( | |
41 | string arg1_str, | |
42 | reg [63:0] arg2_64bits, | |
43 | reg [63:0] arg3_64bits | |
44 | ); | |
45 | task intp ( | |
46 | reg [5:0] tid = 0, | |
47 | reg [63:0] type = 0, | |
48 | reg [63:0] vec = 0, | |
49 | integer src = 16, | |
50 | integer wait = 0 | |
51 | ); | |
52 | task dump_mem ( | |
53 | reg [63:0] addr = 0, | |
54 | integer amount = 8 | |
55 | ); | |
56 | task extint ( | |
57 | integer wait = 0, | |
58 | integer width = 0 | |
59 | ); | |
60 | task warmrst ( | |
61 | integer wait = 0 | |
62 | ); | |
63 | task cpx_stall ( | |
64 | reg [7:0] ccxPortMask = 0, | |
65 | integer length = 0, | |
66 | integer wait = 0 | |
67 | ); | |
68 | task store ( | |
69 | reg [7:0] ccxPortMask = 0, | |
70 | reg [63:0] addr = 0, | |
71 | reg [63:0] data = 0 | |
72 | ); | |
73 | ||
74 | //for counting traps taken in random | |
75 | task L2ErrTrapCount(reg [8:0] count=0); | |
76 | ||
77 | ||
78 | //random Error Injection in CCM: L2 Data Array | |
79 | task L2DAErrInjection(integer injectErr=0); | |
80 | ||
81 | //random Error Injection in CCM: L2 TAG Array | |
82 | task L2TAErrInjection(integer errorinject=0); | |
83 | ||
84 | task siuDmaRd(reg [63:0] addr=0, | |
85 | integer amount=0); | |
86 | ||
87 | task siuDmaWri(reg [63:0] addr=0, | |
88 | integer amount=0); | |
89 | ||
90 | task siuDmaWr8(reg [63:0] addr=0, | |
91 | reg [63:0] data=0, | |
92 | reg [63:0] size=0); | |
93 | ||
94 | task jtagRdWrL2(reg [63:0] paAddr=0, | |
95 | reg [63:0] data=0, | |
96 | reg [63:0] jtagDoneAddrMem=0, | |
97 | reg rdwr=0); | |
98 | ||
99 | task IosErrInj (string errtype, bit [15:0] ctag, bit [39:0] pa); | |
100 | task IosRandErrInj (string errtype, integer num_errs, integer weight); | |
101 | ||
102 | task pktGenConfig(integer mac_port, integer frame_type, integer frame_class, integer data_length, | |
103 | (integer tx_multi_port = 0, integer data_length_p1 = -1)); | |
104 | ||
105 | task NIU_SetTxRingKick (integer mac_port, integer dma_no, | |
106 | (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)); | |
107 | ||
108 | task NIU_AddTxChannels (integer mac_port, integer dma_no, | |
109 | (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)); | |
110 | ||
111 | task NIU_SetTxMaxBurst (integer mac_port, integer dma_no, integer SetTxMaxBurst_Data, | |
112 | (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)); | |
113 | ||
114 | task NIU_TxDMAActivate (integer mac_port, integer dma_activelist, | |
115 | (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)); | |
116 | ||
117 | task NIU_InitTxDma (integer mac_port, integer dma_no, bit Xlate, | |
118 | (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)); | |
119 | ||
120 | task NIU_EXIT_chk (integer mac_port); | |
121 | ||
122 | task TxPktGen (integer mac_port, integer dmaport, integer numofpacket, | |
123 | (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)); | |
124 | ||
125 | task NIU_InitRxDma (integer RxDmaChnlNo, | |
126 | integer RxDescRingLen, | |
127 | bit [39:0] RxRingStartAddr, | |
128 | bit [63:0] RbrConfData, | |
129 | integer RxInitKick, | |
130 | bit Xlate, | |
131 | (bit [15:0] rx_multi_dma = 16'h0)); | |
132 | ||
133 | task NIU_RxPktConf (integer RxPktCnt, (integer iport = 0)); | |
134 | ||
135 | task NIU_RxGenPkt (integer mac_port, | |
136 | integer RxDmaChnlNo, | |
137 | integer RxPktCnt, | |
138 | integer RxPktLen, | |
139 | (integer rx_multi_PORT=0, bit [15:0] rx_multi_DMA= 16'h0)); | |
140 | ||
141 | task errCpxPkt(reg [2:0] tid, | |
142 | reg [3:0] type, | |
143 | reg [1:0] errBits, | |
144 | reg [1:0] ifill2 = 0, | |
145 | reg [63:0] addr = 64'hffffffffffffffff, | |
146 | reg ncValue=0); | |
147 | ||
148 | ||
149 | task IC_hard_err_inj(reg [3:0] err_type, | |
150 | reg [48:0] va, | |
151 | reg [2:0] way=0, | |
152 | reg [7:0] tid=~0); | |
153 | ||
154 | task DC_hard_err_inj(reg [3:0] err_type, | |
155 | reg [6:0] index, | |
156 | reg [1:0] way=0, | |
157 | reg [7:0] tid=~0); | |
158 | ||
159 | task DTLB_err_enable(bit [2:0] err_type=~0, | |
160 | integer err_freq=-1, | |
161 | bit [1:0] merr=~0, | |
162 | integer burst_len=-1, | |
163 | integer burst_freq=-1, | |
164 | bit [7:0] tid=~0); | |
165 | ||
166 | task ITLB_err_enable(bit [2:0] err_type=~0, | |
167 | integer err_freq=-1, | |
168 | bit [1:0] merr=~0, | |
169 | integer burst_len=-1, | |
170 | integer burst_freq=-1, | |
171 | bit [7:0] tid=~0); | |
172 | ||
173 | task DC_err_enable(bit [3:0] err_type=~0, | |
174 | integer err_freq=-1, | |
175 | bit [1:0] merr=~0, | |
176 | integer burst_len=-1, | |
177 | integer burst_freq=-1, | |
178 | bit [7:0] tid=~0); | |
179 | ||
180 | task STB_err_enable(bit [4:0] err_type=~0, | |
181 | integer err_freq=-1, | |
182 | bit [1:0] merr=~0, | |
183 | integer burst_len=-1, | |
184 | integer burst_freq=-1, | |
185 | bit [1:0] ue_en=~0, | |
186 | integer ce_wt=-1, | |
187 | bit [7:0] tid=~0); | |
188 | ||
189 | task L2C_err_enable(bit [5:0] err_type=~0, | |
190 | integer err_freq=-1, | |
191 | integer ce_wt=-1, | |
192 | integer nd_wt=-1, | |
193 | integer burst_len=-1, | |
194 | integer burst_freq=-1, | |
195 | bit [7:0] tid=~0); | |
196 | ||
197 | task IRF_err_enable(bit [2:0] err_type=~0, | |
198 | integer err_freq=-1, | |
199 | integer ce_wt=-1, | |
200 | reg [1:0] merr=~0, | |
201 | integer burst_len=-1, | |
202 | integer burst_freq=-1, | |
203 | bit [7:0] tid=~0); | |
204 | ||
205 | task FRF_err_enable(bit [2:0] err_type=~0, | |
206 | integer err_freq=-1, | |
207 | integer ce_wt=-1, | |
208 | reg [1:0] merr=~0, | |
209 | integer burst_len=-1, | |
210 | integer burst_freq=-1, | |
211 | bit [7:0] tid=~0); | |
212 | ||
213 | ||
214 | task MRA_err_enable(bit [1:0] err_type=~0, | |
215 | integer err_freq=-1, | |
216 | reg [7:0] mra_entry=~0, | |
217 | reg [1:0] wr_en=~0, | |
218 | integer burst_len=-1, | |
219 | integer burst_freq=-1, | |
220 | bit [7:0] tid=~0); | |
221 | ||
222 | task SCA_err_enable(integer err_freq=-1, | |
223 | integer ce_wt=-1, | |
224 | integer burst_len=-1, | |
225 | integer burst_freq=-1, | |
226 | bit [7:0] tid=~0); | |
227 | ||
228 | task TSA_err_enable(bit [1:0] err_type=~0, | |
229 | integer err_freq=-1, | |
230 | reg [6:0] tsa_entry=~0, | |
231 | reg [1:0] wr_en=~0, | |
232 | integer ce_wt=-1, | |
233 | integer burst_len=-1, | |
234 | integer burst_freq=-1, | |
235 | bit [7:0] tid=~0); | |
236 | ||
237 | task TCC_err_enable(bit [1:0] err_type=~0, | |
238 | integer err_freq=-1, | |
239 | integer ce_wt=-1, | |
240 | integer burst_len=-1, | |
241 | integer burst_freq=-1, | |
242 | bit [7:0] tid=~0); | |
243 | ||
244 | task IC_err_enable(bit [3:0] err_type=~0, | |
245 | integer err_freq=-1, | |
246 | bit [1:0] merr=~0, | |
247 | integer burst_len=-1, | |
248 | integer burst_freq=-1, | |
249 | bit [7:0] tid=~0); | |
250 | ||
251 | task registerSlam(string registerName, | |
252 | reg[127:0] value, | |
253 | reg[63:0] tidMask); | |
254 | ||
255 | task marker(string what, reg [5:0] fromTid, reg [63:0] pc); | |
256 | ||
257 | task reset_now(string what); | |
258 | ||
259 | ||
260 | task set_StartPEUTest (); | |
261 | ||
262 | task EnablePCIeEgCmd (string cmdType, | |
263 | bit [63:0] addr, | |
264 | bit [31:0] txLen, | |
265 | bit [31:0] startData, | |
266 | string err); | |
267 | ||
268 | task EnablePCIeIgCmd (string cmdType, | |
269 | bit [63:0] StartAddr, | |
270 | bit [63:0] EndAddr, | |
271 | // bit [31:0] txLen, | |
272 | string txLen, | |
273 | bit [31:0] NumCmdss, | |
274 | string err); | |
275 | ||
276 | ||
277 | task watchDebugReg(integer which, integer wait=0, | |
278 | reg verbose=0, reg [1:0] checkValue); | |
279 | ||
280 | task spc_warm_reset(); | |
281 | ||
282 | ||
283 | } | |
284 | ||
285 | #endif |