Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ios_ras_ports_binds.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC__IOS_RAS_PORTS_BINDS_VRH | |
36 | #define INC__IOS_RAS_PORTS_BINDS_VRH | |
37 | ||
38 | #include "top_defines.vrh" | |
39 | ||
40 | port niu_sii_inj_port { | |
41 | clk; | |
42 | req_vld; | |
43 | data; | |
44 | // hdr; | |
45 | parity; | |
46 | } | |
47 | ||
48 | bind niu_sii_inj_port niu_sii_inj_bind { | |
49 | clk niu_sii_inj.clk; | |
50 | req_vld niu_sii_inj.req; | |
51 | data niu_sii_inj.data; | |
52 | // hdr niu_sii_inj.hdr; | |
53 | parity niu_sii_inj.parity; | |
54 | } | |
55 | ||
56 | port sio_niu_inj_port { | |
57 | clk; | |
58 | req_vld; | |
59 | data; | |
60 | parity; | |
61 | } | |
62 | ||
63 | bind sio_niu_inj_port sio_niu_inj_bind { | |
64 | clk sio_niu_inj.clk; | |
65 | req_vld sio_niu_inj.req; | |
66 | data sio_niu_inj.data; | |
67 | parity sio_niu_inj.parity; | |
68 | } | |
69 | ||
70 | port dmu_sii_inj_port { | |
71 | clk; | |
72 | req_vld; | |
73 | data; | |
74 | parity; | |
75 | be_parity; | |
76 | wrack_vld; | |
77 | wrack_tag; | |
78 | wrack_par; | |
79 | } | |
80 | ||
81 | bind dmu_sii_inj_port dmu_sii_inj_bind { | |
82 | clk dmu_sii_inj.clk; | |
83 | req_vld dmu_sii_inj.req; | |
84 | data dmu_sii_inj.data; | |
85 | parity dmu_sii_inj.parity; | |
86 | be_parity dmu_sii_inj.be_parity; | |
87 | wrack_vld dmu_sii_inj.wrack_vld; | |
88 | wrack_tag dmu_sii_inj.wrack_tag; | |
89 | wrack_par dmu_sii_inj.wrack_par; | |
90 | } | |
91 | ||
92 | port sio_dmu_inj_port { | |
93 | clk; | |
94 | req_vld; | |
95 | data; | |
96 | parity; | |
97 | } | |
98 | ||
99 | bind sio_dmu_inj_port sio_dmu_inj_bind { | |
100 | clk sio_dmu_inj.clk; | |
101 | req_vld sio_dmu_inj.req; | |
102 | data sio_dmu_inj.data; | |
103 | parity sio_dmu_inj.parity; | |
104 | } | |
105 | ||
106 | port l2_sio_inj_port { | |
107 | clk; | |
108 | ctag_vld; | |
109 | data; | |
110 | parity; | |
111 | ue_err; | |
112 | } | |
113 | ||
114 | .for($b=0; $b<8; $b++) { | |
115 | bind l2_sio_inj_port l2_${b}_sio_inj_bind { | |
116 | clk l2_${b}_sio_inj.clk; | |
117 | ctag_vld l2_${b}_sio_inj.ctag_vld; | |
118 | data l2_${b}_sio_inj.data; | |
119 | parity l2_${b}_sio_inj.parity; | |
120 | ue_err l2_${b}_sio_inj.ue_err; | |
121 | } | |
122 | .} | |
123 | ||
124 | port sii_ncu_inj_port { | |
125 | clk; | |
126 | gnt; | |
127 | req; | |
128 | data; | |
129 | parity; | |
130 | } | |
131 | ||
132 | bind sii_ncu_inj_port sii_ncu_inj_bind { | |
133 | clk sii_ncu_inj.clk; | |
134 | gnt sii_ncu_inj.gnt; | |
135 | req sii_ncu_inj.req; | |
136 | data sii_ncu_inj.data; | |
137 | parity sii_ncu_inj.parity; | |
138 | } | |
139 | ||
140 | #endif |