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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ilu_iil_bufmgr.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_ilu_iil_bufmgr ( | |
36 | clk, | |
37 | rst_l, | |
38 | p2d_ihb_wptr, | |
39 | d2p_ihb_addr, | |
40 | ihb_rptr_inc, | |
41 | ihb_empty, | |
42 | ||
43 | // debug | |
44 | ihb_rptr, | |
45 | ihb_wptr); | |
46 | ||
47 | //synopsys sync_set_reset "rst_l" | |
48 | ||
49 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
50 | ||
51 | //--------------------------------------------------------------------- | |
52 | // Clock and Reset Signals | |
53 | //--------------------------------------------------------------------- | |
54 | input clk; // input clock | |
55 | input rst_l; // input reset | |
56 | ||
57 | //--------------------------------------------------------------------- | |
58 | // IHB and IHB management interface | |
59 | //--------------------------------------------------------------------- | |
60 | input [6:0] p2d_ihb_wptr; // gray-coded IHB write pointer | |
61 | output [5:0] d2p_ihb_addr; // binary read pointer to IHB | |
62 | ||
63 | //--------------------------------------------------------------------- | |
64 | // IIL internal interface | |
65 | //--------------------------------------------------------------------- | |
66 | input ihb_rptr_inc; // advance d2p_ihb_addr, from *_xfrfsm.v | |
67 | output ihb_empty; // to *_xfrfsm.v | |
68 | ||
69 | //--------------------------------------------------------------------- | |
70 | // debug signals | |
71 | //--------------------------------------------------------------------- | |
72 | output [6:0] ihb_rptr; // binary IHB read pointer | |
73 | output [6:0] ihb_wptr; // binary IHB write pointer | |
74 | ||
75 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
76 | ||
77 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
78 | reg [6:0] ihb_rptr; // binary IHB read pointer | |
79 | ||
80 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
81 | wire [6:0] gray_ihb_wptr; // gray-coded IHB write pointer | |
82 | ||
83 | // >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
84 | ||
85 | // 0in known_driven -var ihb_rptr_inc | |
86 | ||
87 | // >>>>>>>>>>>>>>>>>>>>>>>>> Function Declarations <<<<<<<<<<<<<<<<<<<<<<<<<< | |
88 | ||
89 | // converts gray-coded to binary-coded | |
90 | function [6:0] gray2bin; | |
91 | input [6:0] gray; | |
92 | reg temp; | |
93 | integer i; | |
94 | begin | |
95 | temp = 0; | |
96 | for (i=6; i>=0; i=i-1) begin | |
97 | temp = temp ^ gray[i]; | |
98 | gray2bin[i] = temp; | |
99 | end | |
100 | end | |
101 | endfunction // gray2bin | |
102 | ||
103 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< | |
104 | ||
105 | assign ihb_empty = (ihb_rptr == ihb_wptr); | |
106 | assign ihb_wptr = gray2bin(gray_ihb_wptr); | |
107 | assign d2p_ihb_addr = ihb_rptr[5:0]; | |
108 | ||
109 | always @ (posedge clk) | |
110 | if (!rst_l) begin | |
111 | ihb_rptr <= 7'b0; | |
112 | end | |
113 | else if(ihb_rptr_inc) begin | |
114 | ihb_rptr <= ihb_rptr + 1'b1; | |
115 | end | |
116 | ||
117 | // ******************************** Instantiation ************************ | |
118 | // sync flops | |
119 | // pcie_common_sync_flop #(7) sync_flop ( | |
120 | // .clk(clk), | |
121 | // .din(p2d_ihb_wptr), | |
122 | // .dout(gray_ihb_wptr)); | |
123 | cl_a1_clksyncff_4x sync_flop_6 ( .d(p2d_ihb_wptr[6]), .si(1'b0), .q( gray_ihb_wptr[6]), .so(), | |
124 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); | |
125 | cl_a1_clksyncff_4x sync_flop_5 ( .d(p2d_ihb_wptr[5]), .si(1'b0), .q( gray_ihb_wptr[5]), .so(), | |
126 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); | |
127 | cl_a1_clksyncff_4x sync_flop_4 ( .d(p2d_ihb_wptr[4]), .si(1'b0), .q( gray_ihb_wptr[4]), .so(), | |
128 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); | |
129 | cl_a1_clksyncff_4x sync_flop_3 ( .d(p2d_ihb_wptr[3]), .si(1'b0), .q( gray_ihb_wptr[3]), .so(), | |
130 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); | |
131 | cl_a1_clksyncff_4x sync_flop_2 ( .d(p2d_ihb_wptr[2]), .si(1'b0), .q( gray_ihb_wptr[2]), .so(), | |
132 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); | |
133 | cl_a1_clksyncff_4x sync_flop_1 ( .d(p2d_ihb_wptr[1]), .si(1'b0), .q( gray_ihb_wptr[1]), .so(), | |
134 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); | |
135 | cl_a1_clksyncff_4x sync_flop_0 ( .d(p2d_ihb_wptr[0]), .si(1'b0), .q( gray_ihb_wptr[0]), .so(), | |
136 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); | |
137 | ||
138 | endmodule // dmu_ilu_iil_bufmgr | |
139 | ||
140 | ||
141 |